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31. 发明专利

JPS59231955A SIGNAL TRANSMISSION CIRCUIT 失效
公开(公告)号：JPS59231955A
公开(公告)日：1984-12-26
申请号：JP10699883
申请日：1983-06-15
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： KOUDA YOSHIO , YAZAWA KATSUHIKO , NISHIKADO IWAMASA , HIMENO RIYOUICHI
IPC分类号： H04L13/08 , H04L12/00
摘要： PURPOSE:To realize asynchronously the data transmission/reception between devices by utilizing the characteristic of an FIFO not requiring a read/write address and transmitting a signal in the unit of plural words between the devices not using nay RAM, to simplify the constitution of a signal transmission circuit. CONSTITUTION:The FIFO (F) inputting a data input and a shift signal SI is provided between a device A at the data transmission side and a device B at data reception side, a data output is outputted to the device B from the FIFO and also a shift-out signal SO is added to the FIFO from the device B. Further, an up-down counter C inputting an up-signal UP from the device A and a down-signal DN from the device B is provided between the devices A, B. Moreover, the counter C is incremented when a signal for one packet's share is inputted to the FIFO, and every time the signal of one packet is outputted, the output is displayed backward on the devices A, B and the signal in the unit of plural words is transmitted between the devices A, B with simple constitution.

32. 发明专利

JPS57130150A REGISTER CONTROL SYSTEM 失效
公开(公告)号：JPS57130150A
公开(公告)日：1982-08-12
申请号：JP1472381
申请日：1981-02-03
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAZAWA KATSUHIKO , OKADA KATSUYUKI
IPC分类号： G06F9/38 , G06F9/30 , G06F9/34
摘要： PURPOSE:To obtain a control system where the instruction execution time is shortened, by reading and writing data to and from a general register in the first half and the latter of the same operation cycle respectively. CONSTITUTION:In respect to a means which writes the operation result of a preceding instruction to a general register and reads a succeeding instruction in the indexing cycle in the same operation cycle, the operation result of the preceding instruction is stored from an operating circuit ALU to an operation result storage buffer register RBR when the operation execution cycle is terminated. Next, contents of the register RBR are written to a register REG1 through a bus PB in the latter half of the operation result write cycle, and a general register write control signal Wt is transmitted from a control circuit CTL to the register REG1 to control the write. In the indexing cycle, a general register read control signal Rt is sent from the control circuit CTL to the register REG1 to tead control data from the register REG1.

33. 发明专利

JPS5419627A COLLATION SYSTEM FOR DATA PROCESSING UNIT 失效
公开(公告)号：JPS5419627A
公开(公告)日：1979-02-14
申请号：JP8486577
申请日：1977-07-14
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： SEO TOMIHIDE , YAZAWA KATSUHIKO , NIWA AKIO
IPC分类号： G06F11/18 , G06F15/16 , G06F15/177
摘要： PURPOSE:To reduce the lead wires from each data processing unit, by picking up the collation data in the form of concentration, and to realize the collation to the external unit control section and the control section while minimizing the decrease in the lead wires.

34. 发明专利

JPS57109056A INTERRUPTION CONTROL SYSTEM 失效
公开(公告)号：JPS57109056A
公开(公告)日：1982-07-07
申请号：JP18559480
申请日：1980-12-26
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： YAZAWA KATSUHIKO , TOKUNAGA YASUSHI
IPC分类号： G06F9/48
摘要： PURPOSE:To vary a vector level instantaneously and to simplify an interruption processing program, by referring to the vector level at any time by installing a control part for the vector level at a common processing part. CONSTITUTION:In an interruption level register VL0 in the common control part CPR of a data processing system which has a vector interrupting function, a level for uniforming the acceptance of write requests is set. When external devices EXTPo-EXTPn connected to the control part CPR have interruption requests, an interruption-request cause FFIS is set and an interruption level is set by the FFIS in a generating circuit VL1 for interruption levels which correspond to interruption causes. In this state, the levels of the register VL0 and circuit VL1 are compared mutually by a comparing circuit COMP; when VL0> VL1, the interruption request is rejected and when VL0

35. 发明专利

JPH0210999A INCOMING CALL DISTRIBUTION SYSTEM 失效
公开(公告)号：JPH0210999A
公开(公告)日：1990-01-16
申请号：JP16196888
申请日：1988-06-28
申请人： MEISEI ELECTRIC CO LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP
发明人： HOJO KATSUO , KANO TAKASHI , YAZAWA KATSUHIKO
IPC分类号： H04Q3/58 , H04Q5/00
摘要： PURPOSE:To improve the line efficiency by identifying incoming telephone number information at an incoming state in a intelligent service digital network and giving a call to a reception terminal equipment or a terminal equipment group corresponding thereto. CONSTITUTION:When a call comes from a digital line 1k, control information required for the incoming control is sent to an exchange system 3 via a corresponding digital service unit 2k. Then said data channel control information is demultiplexed in the corresponding trunk 31k and inputted to a central processing unit 34. The processing unit 34 detects incoming telephone number information DN- from the received control information to discriminate whether it is information DN1 to designate a #1 reception terminal group TMQ1 or not. When the information DN- is the information DN1, the processing unit 34 selects the terminal group TMQ1 and selects an idle terminal equipment 41r in the received terminal equipments. Through the selective operation, the line 1k is connected to the terminal equipment 41r to attain communication.

36. 发明专利

JPS5846425A KEY SCANNING SYSTEM 失效
公开(公告)号：JPS5846425A
公开(公告)日：1983-03-17
申请号：JP14325681
申请日：1981-09-11
申请人： NIPPON ELECTRIC CO
发明人： YAZAWA KATSUHIKO , OOKAWA KAZUMASA
IPC分类号： G06F3/023 , H03K5/1254 , H03M11/20
摘要： PURPOSE:To absorb chatter of a multicontact key signal and to convert the key signal into a digital signal easily by scanning the key signal with the counter value of a clock signal, and then outputting a key number once the key signal becomes stable. CONSTITUTION:The counter value of a counter circuit CNT synchronizing with a clock signal QII is equalized to one of the numbers of keys Key0-Key7, and a key signal is scanned by the counter value. When the key signal is generated, the counter CNT is stopped by a signal from a scanning circuit and the key number is outputted once the key signal becomes stable. Then, the counter CNT is put in operation again to discriminate by scanning whether other keys are operated or not. Thus, said operation is repeated to convert the key signal into a digital signal.

37. 发明专利

JPS5843036A BUFFER CONTROLLER 失效
公开(公告)号：JPS5843036A
公开(公告)日：1983-03-12
申请号：JP14117981
申请日：1981-09-08
申请人： NIPPON ELECTRIC CO
发明人： YAZAWA KATSUHIKO , OOKAWA KAZUMASA
IPC分类号： G06F5/16 , G06F5/06
摘要： PURPOSE:To improve the transfer performance up to an input speed, by using a buffer having plural face and accordingly excluding the transfer of data among the buffers. CONSTITUTION:A control circuit CTL is started with a control signal C.IN, and a control circuit CTL decides a buffer to which an input data D.IN is fed. If a buffer BF0 is idle, a signal W0 is delivered from the circuit CTL. Thus a writing address control circuit ADEC0 is actuated to write the data D.IN successively to the buffer BF0. When the buffer BF0 is filled, a signal W1 is delivered from the circuit CTL. Thus an address control circuit ADEC1 is actuated to write the data D.IN to a buffer BF1. The information is transmitted from an output terminal D.OUT simultaneously with the writing of the data D.IN.

38. 发明专利

JPS5748150A Common memory control system 失效
标题翻译：通用记忆控制系统
公开(公告)号：JPS5748150A
公开(公告)日：1982-03-19
申请号：JP12189880
申请日：1980-09-03
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： FUKUSHIMA TOMOYOSHI , MIKI SHIYUUJI , MASUO KAZUYUKI , NIHEI TOSHIHIKO , YAZAWA KATSUHIKO , IWAMOTO YOSHIHARU
IPC分类号： G06F12/00 , G06F13/18 , G06F15/16 , G06F15/167
CPC分类号： G06F13/18
摘要： PURPOSE:To shorten the bus length and to reduce the bus delay, by dividing plural processors into plural groups, connecting the respective processors to a common bus, selecting an access request from the processor in the group, and accessing a memory circuit. CONSTITUTION:Selecting circuits SLo-SLm select an access request signal rq from a processor in each group #o-#m, output a bsy signal busy, and also send out a response signal and to a processor which has received the access request. Also, a selecting circuit SL selects the signal bsy from the circuits SLo-SLm of the respective interface circuits INFo-INFm in the same way as the concurrent selection of the access request signal, sends out a response signal (an) to a bus interface circuit corresponding to the received signal bys, and also sends out a timing signal (t) for controlling the bus. A memory controlling circuit MC starts a memory circuit M when the signal (an) is sent out from the circuit SL.
摘要翻译：目的：为了缩短总线长度并减少总线延迟，通过将多个处理器分成多个组，将各个处理器连接到公共总线，从组中的处理器中选择访问请求，并访问存储器电路。构成：选择电路SLo-SLm从每个组＃o＃＃m中的一个处理器中选择一个访问请求信号rq，输出一个bsy信号忙，并发送一个响应信号和一个接收到访问请求的处理器。此外，选择电路SL以与接入请求信号的并发选择相同的方式从各个接口电路INFo-INFm的电路SLo-SLm中选择信号bsy，并将响应信号（a）发送到总线接口电路对应于接收信号，并且还发出用于控制总线的定时信号（t）。当从电路SL发出信号（a）时，存储器控制电路MC启动存储电路M.

39. 发明专利

JPS5952414A Fast-forward reproduction control system 失效
标题翻译：快进再生控制系统
公开(公告)号：JPS5952414A
公开(公告)日：1984-03-27
申请号：JP16117982
申请日：1982-09-16
申请人： Fujitsu Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： KUNIYOSHI SHIYUUICHI , KIMURA AKIO , SHINOOKA MAKOTO , OOYAMA MINORU , YAZAWA KATSUHIKO , FUKUI AKIRA
IPC分类号： H04M11/10 , G11B20/10 , H04M3/50 , H04M3/533
CPC分类号： H04M3/533
摘要： PURPOSE:To make a speedy program search of a desired message and listen to it in a short time, and to shorten a reproduction time and improve use efficiency, by controlling the rapid traverse reproduction of a digital voice storage reproducing device that is used in common by many subscribers. CONSTITUTION:A voice signal inputted from a telephone set 1 is compressed on silent basis and stored and held in a voice storage reproducing device 9. A reproduction request signal is received by a buffer memory device 6 and data to be reproduced by a recording device 8 or 8' is transferred to the buffer memory for reproduction of the memory device 6 and reproduced by the codes 5 of a trunk 4 to be sent to the telephone set 1 through exchanges 3 and 2. Further, the information after the silent compression and storage is reproduced while thinned out at specific intervals of time, speeding up the operation.
摘要翻译：目的：通过控制共同使用的数字语音存储再现装置的快速遍历再现，使得在短时间内快速地搜索期望的消息并收听它，并缩短再现时间并提高使用效率由许多用户。构成：从电话机1输入的语音信号以静音方式被压缩并存储并保存在语音存储再现装置9中。再现请求信号由缓冲存储装置6接收，数据由记录装置8再现或8'被传送到缓冲存储器以用于存储器件6的再现，并由中继线4的代码5再现，以通过交换器3和2发送到电话机1.此外，静音压缩和存储之后的信息在特定的时间间隔被稀释再现，加快了操作。

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