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1. 发明专利

JPS5952414A Fast-forward reproduction control system 失效
标题翻译：快进再生控制系统
公开(公告)号：JPS5952414A
公开(公告)日：1984-03-27
申请号：JP16117982
申请日：1982-09-16
申请人： Fujitsu Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： KUNIYOSHI SHIYUUICHI , KIMURA AKIO , SHINOOKA MAKOTO , OOYAMA MINORU , YAZAWA KATSUHIKO , FUKUI AKIRA
IPC分类号： H04M11/10 , G11B20/10 , H04M3/50 , H04M3/533
CPC分类号： H04M3/533
摘要： PURPOSE:To make a speedy program search of a desired message and listen to it in a short time, and to shorten a reproduction time and improve use efficiency, by controlling the rapid traverse reproduction of a digital voice storage reproducing device that is used in common by many subscribers. CONSTITUTION:A voice signal inputted from a telephone set 1 is compressed on silent basis and stored and held in a voice storage reproducing device 9. A reproduction request signal is received by a buffer memory device 6 and data to be reproduced by a recording device 8 or 8' is transferred to the buffer memory for reproduction of the memory device 6 and reproduced by the codes 5 of a trunk 4 to be sent to the telephone set 1 through exchanges 3 and 2. Further, the information after the silent compression and storage is reproduced while thinned out at specific intervals of time, speeding up the operation.
摘要翻译：目的：通过控制共同使用的数字语音存储再现装置的快速遍历再现，使得在短时间内快速地搜索期望的消息并收听它，并缩短再现时间并提高使用效率由许多用户。构成：从电话机1输入的语音信号以静音方式被压缩并存储并保存在语音存储再现装置9中。再现请求信号由缓冲存储装置6接收，数据由记录装置8再现或8'被传送到缓冲存储器以用于存储器件6的再现，并由中继线4的代码5再现，以通过交换器3和2发送到电话机1.此外，静音压缩和存储之后的信息在特定的时间间隔被稀释再现，加快了操作。

2. 发明专利

JPS59160256A Processor controlling system 失效
标题翻译：处理器控制系统
公开(公告)号：JPS59160256A
公开(公告)日：1984-09-10
申请号：JP3425683
申请日：1983-03-02
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： TOBE YOSHIHARU , YASHIRO ZENICHI , NISHIWAKI MINEO , KUNIYOSHI SHIYUUICHI
IPC分类号： G06F15/16 , G06F13/36 , G06F15/163 , G06F15/177
CPC分类号： G06F15/177
摘要： PURPOSE:To simplify the constitution of a circuit by connecting one master processor and plural slave processors to one set of common bus, sending out a maintenance packet from the master processor, and selecting the slave processor. CONSTITUTION:When a master processor 1 controls a slave processor 2, in accordance with an instruction of the master processor 1, a bus interface circuit of the master processor 1 generates a maintenance packet containing a processor number of the slave processor to be controlled, and a command and sends it out to a system bus 5. The bus interface circuit 3 of the slave processor 2 receives the maintenance packet from the system bus 5, and when a processor number contained in said packet coincides with its own number, a command code is decoded, and the slave processor 2 is controlled through a control line 7. In this way, the constitution of a circuit is simplified, and the slave processors are extended easily.
摘要翻译：目的：通过将一个主处理器和多个从属处理器连接到一组公共总线来简化电路的结构，从主处理器发送维护包，并选择从属处理器。构成：当主处理器1控制从属处理器2时，根据主处理器1的指令，主处理器1的总线接口电路产生包含待控制的从属处理器的处理器编号的维护包，以及命令并将其发送到系统总线5.从处理器2的总线接口电路3从系统总线5接收维护分组，并且当包含在所述分组中的处理器号码与其自身号码一致时，命令代码被解码，从处理器2通过控制线路7进行控制。这样，简化了电路的结构，并且容易地扩展从处理器。

3. 发明专利

JPS59158422A Information transfer and control system 失效
标题翻译：信息传递与控制系统
公开(公告)号：JPS59158422A
公开(公告)日：1984-09-07
申请号：JP3180683
申请日：1983-03-01
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： YASHIRO ZENICHI , HONDA TAKASHI , TOBE YOSHIHARU , KUNIYOSHI SHIYUUICHI
IPC分类号： G06F13/36 , G06F3/00
摘要： PURPOSE: To obtain an information transfer control system with less number of communication bus lines by using a communication bus and transferring transmission status information after transmitting transfer information from a transferring data processor to a destination data processor.
CONSTITUTION: The transfer information on a main storage device 6 is transferred to a transmission high speed buffer 10-1 by a start instruction from a central controller 5. When the use of the communication bus 2 is permitted, the content of an address register 8 storing an address of a data processor being an opposite party of communication is transmitted to the bus 2. When the content of the bus 2 is addressed to itself, each data processor starts a receiving DMA (direct memory access) circuit 9-2 to receive the data and a transmission DMA circuit 9-1 transfers the data in the buffer 10-1 in succession to the address. When a parity error and a transmission underrun are detected, its cause is set to a transmission status register 12-1. The content of the register 12-1 is transferred to the data processor of the opposite party when the data is transmitted.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过使用通信总线获取数量少的通信总线的信息传输控制系统，并将传输信息从传输数据处理器传送到目标数据处理器之后传送传输状态信息。构成：主存储装置6上的传送信息通过来自中央控制器5的开始指令传送到发送高速缓冲器10-1。当允许使用通信总线2时，地址寄存器8的内容存储作为通信对方的数据处理器的地址被发送到总线2.当总线2的内容寻址到其自身时，每个数据处理器启动接收DMA（直接存储器访问）电路9-2以接收数据和传输DMA电路9-1连续地传送缓冲器10-1中的数据到地址。当检测到奇偶校验错误和传输欠载时，其原因被设置为传输状态寄存器12-1。当发送数据时，寄存器12-1的内容被传送到对方的数据处理器。

4. 发明专利

JPS6074174A MEMORY ACCESS SYSTEM 失效
公开(公告)号：JPS6074174A
公开(公告)日：1985-04-26
申请号：JP18142583
申请日：1983-09-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ABE HIDEO , KUNIYOSHI SHIYUUICHI , TONAMI SHIYUUICHI , YASHIRO ZENICHI
IPC分类号： G06F12/02 , G11C7/00 , G11C11/41
摘要： PURPOSE:To execute efficiently a memory access of a system in which plural devices execute an access to a main memory through a common bus, by providing a storage element having a nibble mode, on the main memory, and executing a high speed access by the nibble mode only with regard to a device which requires a high speed access. CONSTITUTION:In figure, 2 is a device which requires a high speed access and to which an access can be executed in a nibble mode, and 4 and 5 are nibble mode impossible devices which require no high speed access. 10 of a main memory 1 is a memory control part, and 11 is a storage element having the nibble mode. An access request to the main memory 1 from the devices 2, 4 and 5 is received by a bus request concurrence preventing circuit 6, and a contention of a request of a common bus 3 is prevented. The device 2 sends a nibble mode control signal to the main memory 1 through a nibble mode control bus 31 of the common bus 3, and can make the nibble mode effective, but the devices 4, 5 do not have this interface, cannot make the nibble mode of the main memory 1 effective, and execute a regular access.

5. 发明专利

JPS60139046A CIRCUIT MONITOR SYSTEM 失效
公开(公告)号：JPS60139046A
公开(公告)日：1985-07-23
申请号：JP24873883
申请日：1983-12-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ABE HIDEO , KUNIYOSHI SHIYUUICHI , TOBE YOSHIHARU , ICHIKAWA HIROYUKI
IPC分类号： H04L29/14 , H04L12/26
摘要： PURPOSE:To monitor a communication controller having plural communication circuits without affecting the circuit transmission quality of a line by controlling a monitor bus and a bus gate of a bus switch by a monitor mode selection signal in response to a bus individual gates at a circuit switch part. CONSTITUTION:When a communication controller 1 monitors a circuit 14-n for example, a processor 12 sends a monitor mode selection signal only to a signal line 16-n of a circuit control part 10-n. Then the part 10-n switches the corresponding circuit and connects it to a monitor but 17 according to the indication of the received signal. Then a mode selecting circuit 18 receives a monitor mode selection signal from a signal line 16-n, then sends a signal corresponding to the contents of the mode selection signal to a bus switch part 19. Then the bus 17 is connected to an external maintenance device 2 through the part 19. As a result, the circuit 14-n is switched by a circuit switch part 11-n and connected to a device 2 via the bus 17 and the part 19. Thus monitoring of the circuit is performed.

6. 发明专利

JPS59123351A Test system for voice storage device 失效
标题翻译：语音存储设备测试系统
公开(公告)号：JPS59123351A
公开(公告)日：1984-07-17
申请号：JP22925882
申请日：1982-12-29
申请人： Fujitsu Ltd
发明人： ARIMA SHIYUUHEI , KUNIYOSHI SHIYUUICHI
IPC分类号： H04M3/22 , G10L11/02 , G10L13/00 , H04M3/42 , H04M3/50
CPC分类号： H04M3/50
摘要： PURPOSE:To check surely the normality of a storage device by folding a digital voice signal from a file memory at a line corresponding section to collate the signal with a digital voice signal stored in the file memory. CONSTITUTION:A central controller CC connects the line corresponding section LC of a voice storage device VSE and a subscriber SUB upon request of the subscribe SUB. A line control section LCNT stores a digital voice signal to a magnetic disc device DKU. When the contents of storage are read from the device DKU, the control section LCNT generates a frame pulse and a pulse representing voice/no voice and transmits the pulse to the corresponding section LC. The control section LCNT stores a folded signal to the device DKU. The central controller CC collates a voice signal read from the device DKU with the folded signal.
摘要翻译：目的：通过在线对应部分折叠来自文件存储器的数字语音信号来确定存储设备的正常性，以将信号与存储在文件存储器中的数字语音信号进行比较。构成：中央控制器CC根据订阅SUB的请求连接语音存储设备VSE的线对应部分LC和订户SUB。线控制部LCNT将数字语音信号存储到磁盘装置DKU。当从设备DKU读取存储内容时，控制部分LCNT产生帧脉冲和表示语音/无声音的脉冲，并将脉冲发送到相应的部分LC。控制部分LCNT将折叠信号存储到设备DKU。中央控制器CC将从设备DKU读取的语音信号与折叠信号进行比较。

7. 发明专利

JPS59119394A Normal operation checking system for voice accumulator 失效
标题翻译：语音累加器的正常运行检查系统
公开(公告)号：JPS59119394A
公开(公告)日：1984-07-10
申请号：JP23187382
申请日：1982-12-25
申请人： Fujitsu Ltd
发明人： KUNIYOSHI SHIYUUICHI
IPC分类号： G06F3/16 , G10L13/00 , G10L19/00

8. 发明专利

JPS6076820A SELF-DIAGNOSIS SYSTEM 失效
公开(公告)号：JPS6076820A
公开(公告)日：1985-05-01
申请号：JP18568483
申请日：1983-10-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： UKAI NAOTOSHI , KUNIYOSHI SHIYUUICHI , YASHIRO ZENICHI , TOKI RIYUUICHI
IPC分类号： H04B1/74 , H04B3/46 , H04L29/14
摘要： PURPOSE:To confirm the normalcy of a communication control system of single constitution without giving any effect to a using system, by connecting a control part corresponding to an artificial circuit to a circuit common controller set under a spare state via a switch control part. CONSTITUTION:A circuit common controller 2 and a spare circuit common controller 2-1 are connected to a circuit correspondence control part group 1 containing plural circuit correspondence control parts 1-1 via a switch control part 6. Thus a communication control system of single constitution is obtained including a maintenance operation device 4 which gives the switching control to both controllers 2 and 2-1. An artificial circuit correspondence controller 5 is connected to the part 6 in parallel with the group 1. For diagnosis of the working state of the controller 2-1, the controller 2-1 is connected to the controller 5 by the device 4 via the part 6.

9. 发明专利

JPS59113498A Voice processor 失效
公开(公告)号：JPS59113498A
公开(公告)日：1984-06-30
申请号：JP22338282
申请日：1982-12-20
申请人： Nippon Electric Co , Nippon Telegraph & Telephone , Fujitsu Ltd
发明人： TOJIYAMA TAKASHI , YAZAWA KATSUHIKO , YOSHIDA TAKASHI , MIDORIKAWA AKIHIRO , SASAHARA YUUJIROU , KUNIYOSHI SHIYUUICHI
IPC分类号： G10L13/00 , G10L19/00

10. 发明专利

JPS60171845A BUS ASSIGNMENT SYSTEM 失效
公开(公告)号：JPS60171845A
公开(公告)日：1985-09-05
申请号：JP2770484
申请日：1984-02-16
申请人： FUJITSU LTD
发明人： KUNIYOSHI SHIYUUICHI
IPC分类号： H04L12/28
摘要： PURPOSE:To attain efficient assignment even when the load of a bus is changed by informing a traffic at each terminal device to a microprocessor and rewriting scan information according to a terminal traffic of the preceding period. CONSTITUTION:The microprocessor (MPU) 16 and scan tables 12, 13 are provided to a bus assignment circuit 1 where plural terminals are connected to a bus 3. A scan table selecting section 14 gives any information of the scan tables 12, 13 to a transmission right giving section 11 according to the command of the MPU so as to give the transmission right to each terminal device in the bus 3 and the number of times at each terminal device is counted by a measuring section 15. An operating scan table is exhanged by the command of the MPU at a prescribed, traffic information is read by the measuring section 15 so as to rewrite the scan information of the scan table not it use.

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