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31. 发明专利

JPH09162394A TUNNEL TRANSISTOR AND STORAGE CIRCUIT 失效
公开(公告)号：JPH09162394A
公开(公告)日：1997-06-20
申请号：JP32020095
申请日：1995-12-08
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： G11C11/38 , G11C11/56 , H01L29/78 , H01L29/80
摘要： PROBLEM TO BE SOLVED: To provide a tunnel transistor which has a plurality of negative resistance characteristics by providing a source electrode, a drain electrode and a gate electrode to be formed on a source, a drain and an insulation layer. SOLUTION: When a positive voltage is applied to a drain electrode 8, three n -p tunnel junctions in all between each left edge of P -GaAs connecting areas 9 and the left edge of a P -GaAs drain 3 and channel layers 4 are permitted to be the forward-direction bias wherein negative resistance appears. Two n -p tunnel junctions between the right edge of the p -GaAs connecting areas 9 and the channel layers 4 are permitted to be reverse-direction bias which has low resistance characteristics. Thus, among the n -P tunnel junctions, three tunnel junctions are forward-direction bias, and the two tunnel junctions are reverse-direction bias. Since reverse-direction bias tunnel junction has extremely low resistance compared with forward-direction bias tunnel junction, current between the source 2 and the drain 3 is decided by the tunnel junction characteristics of the high resistance forward-direction bias, and three negative resistance characteristics are permitted to continuously appear.

32. 发明专利

JPH07320633A SEMICONDUCTOR SPIN POLARIZED ELECTRON SOURCE 失效
公开(公告)号：JPH07320633A
公开(公告)日：1995-12-08
申请号：JP11522194
申请日：1994-05-27
申请人： NEC CORP
发明人： BABA TOSHIO , MIZUTA MASASHI , OMORI TSUNEHIKO , KURIHARA YOSHIMASA , NAKANISHI TSUTOMU
IPC分类号： H01J1/34
摘要： PURPOSE:To provide a semiconductor spin polarized electron source from which a large quantity of electrons having high spin polarized degree can be emitted by forming a p-type conductive strained super lattice structure with no lattice relaxation and composed of reciprocally formed well layers and barrier layers as a spin polarized electron generating region on a substrate. CONSTITUTION:A block layer 4 (p-Al0.35Ga0.65As) with smaller electron affinity than that of a substrate 1 is formed on the substrate 1 (p-GaAs). As a spin polarized electron generating region, strained well layers 8 (p-In0.15Ga0.85As) having larger lattice constants than those of the substrate 1 and thickness about electron wavelength or thinner and barrier layers 6 (p-GaAs) having lower valence electron band energy than that of the strained well layers 8 and thickness thin enough to transmit electrons in conduction band can permeate by tunnel effect are reciprocally formed to compose a p-type conductive short cycle strained super lattice structure with no lattice relaxation. Moreover, a surface layer 7 (p -In0.15Ga0.85As) to absorb the curve of the bands is formed on these layers.

33. 发明专利

JPH07263708A TUNNEL TRANSISTOR 失效
公开(公告)号：JPH07263708A
公开(公告)日：1995-10-13
申请号：JP5347094
申请日：1994-03-24
申请人： NEC CORP
发明人： BABA TOSHIO , UEMURA TETSUYA
IPC分类号： H01L29/78 , H01L29/80
摘要： PURPOSE:To provide a tunnel transistor with which a high current density can be obtained and also a high-speed operation can be conducted. CONSTITUTION:The title tunnel transistor is composed of a source region 2 of the first conductivity type formed on a low carrier density substrate 1, a degenerated semiconductor drain region 3 of the conductivity type different from the source region, an atomic layer doping region 4, having the same conductivity as that of the source region and containing ionized impurities of an atomic layer, provided by connecting the source region and the drain region, an insulating layer provided on the atomic layer doping region and a gate electrode 6 formed thereon, a source electrode 7 and a drain electrode 8 provided on the source region and the drain region. As there are high density ionized impurities in the atomic layer doping region, the tunnel junction between the source region and the drain region becomes very narrow, and a large tunnel current is allowed to flow.

34. 发明专利

JPH06334175A TUNNEL TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06334175A
公开(公告)日：1994-12-02
申请号：JP11981193
申请日：1993-05-21
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L29/68 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a tunnel transistor which is suitable for realizing fineness, low-voltage operation, high-current density and differential negative resistance characteristics. CONSTITUTION:This tunnel transistor has the laminated structure of a first semiconductor 2 (source) of one conductivity type, a second semiconductor 3 which is not degenerated, a third semiconductor 4 (drain) having a reverse conductivity type to that of the first semiconductor 2. In addition, a fourth semiconductor 5 composed of a semiconductor having a narrower forbidden bandwidth than that of the foregoing semiconductors and an insulating layer 6 composed of a material having a wider forbidden bandwidth than that thereof and a gate electrode 7 are provided in the exposed surface of the foregoing semiconductors, and a source electrode 8 and a drain electrode 9 are respectively provided in the first semiconductor 2 and the third semiconductor 4 with the formation of ohmic junction.

35. 发明专利

JPH05175514A TUNNEL TRANSISTOR 失效
公开(公告)号：JPH05175514A
公开(公告)日：1993-07-13
申请号：JP34159391
申请日：1991-12-25
申请人： NEC CORP
发明人： BABA TOSHIO , UEMURA TETSUYA
IPC分类号： H01L29/80 , H01L21/337 , H01L21/338 , H01L29/778 , H01L29/808 , H01L29/812
摘要： PURPOSE:To obtain a tunnel transistor which can suppress gate leakage current by providing first and third semiconductors with ohmic electrodes with a fourth semiconductor and its overlaying electrode over exposed surfaces of first and second semiconductors. CONSTITUTION:A substrate 1 is topped with a coupling structure of a first regenerated semiconductor 2 having a one conductivity type, a second regenerated semiconductor 3, and a third regenerated semiconductor 4, and the third semiconductor 9 is doped with an n-type ionization impurity. This causes a modulation dope structure of the hetero junction of the fourth semiconductor 9 and the second semiconductor 3, electron accumulation on the surface of the second semiconductor 3 of low conduction band energy, and formation of an equivalent thin P -n tunnel diode structure between a source and a drain. Therefore, it is unnecessary to use a large gate voltage to accumulate electrons on the second semiconductor 3, and to impress a large forward bias between the source and the gate, so that gate leakage current can be suppressed.

36. 发明专利

JPH0410417A SURFACE TREATMENT OF COMPOUND SEMICONDUCTOR 失效
公开(公告)号：JPH0410417A
公开(公告)日：1992-01-14
申请号：JP11145990
申请日：1990-04-26
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L21/308
摘要： PURPOSE:To clean the surface of compound semiconductor only through a low-temperature treatment by completely remove an oxide film, composed of anion and cation oxide, from the surface of a compound semiconductor substrate, and immersing the substrate until the surface is covered with a film that consists only of anion. CONSTITUTION:An oxide film, composed of gallium oxide and arsenic oxide, is formed on a GaAs substrate. This substrate is immersed in concentrated hydrochloric acid to remove the gallium oxide (cationic oxide) in the oxide film by etching. On the other hand, the arsenic oxide (anionic oxide), not etched, is reduced to arsenic (anion) in the concentrated hydrochloric acid. Therefore, the oxide film on the GaAs substrate is gradually converted to arsenic film in the concentrated hydrochloric acid. After a sufficient period of time, the oxide film is completely replaced by a GaAs film on the substrate. In this way, the compound semiconductor surface becomes free of oxide, and it is covered with an anion deposit having a low evaporating temperature, so that the substrate can be cleaned by a low-temperature heat treatment.

37. 发明专利

JPH01268056A HIGH SPEED TRANSISTOR 失效
公开(公告)号：JPH01268056A
公开(公告)日：1989-10-25
申请号：JP9723388
申请日：1988-04-19
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L29/68 , H01L29/205
摘要： PURPOSE:To eliminate defects of a conventional HET and to obtain a transistor which can operate at a very high speed, by providing a structure wherein an emitter layer, a base layer, a collector barrier layer and a collector layer respectively consisting of specified semiconductors are laminated. CONSTITUTION:The following layers are provided in this structure: a emitter 14 comprising an N-type first semiconductor wherein first and second conduction bands are provided, and energy at the bottom of the second conduction band is lower than the bottom of the first conduction band; a base layer 13 comprising an N-type second semiconductor wherein the bottom of a second conduction band of energy is lower than the bottom of the second conduction band of the emitter layer 14 and the bottom of a first conduction band of energy is lower than the bottom of the second conduction band; a collector barrier layer 12 comprising a low impurity concentration third semiconductor wherein the bottom of a second conduction band of energy is lower than the bottom of the second conduction band of the emitter layer 14 and higher than the bottom of the first conduction band of the base layer 13 and a first conduction band of energy is higher than the bottom of the first conduction band of the base layer 13; and a collector layer 11 comprising an N-type fourth semiconductor.

38. 发明专利

JPS62271464A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62271464A
公开(公告)日：1987-11-25
申请号：JP11376086
申请日：1986-05-20
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/20 , H01L29/72 , H01L29/737
摘要： PURPOSE:To reduce parasitic capacitance, and to operate a semiconductor device at ultra-high speed by burying a collector region into an insulating film so that one part is exposed to the surface, spreading a single crystal region on the surface, using an exposed section as a seed and forming a base region. CONSTITUTION:An N-type GaAs collector layer 2 approximately 5000Angstrom is grown on a GaAs substrate 1, sections except a transistor element region are removed through etching in approximately 1mum, and sections under a transistor operating region are etched as deep as approximately 2000Angstrom . An insulating film 9 is shaped, and flattened so that the surface of the collector layer 2 is exposed. An amorphous GaAs layer is formed onto the surface through a molecular-beam epitaxial method, and changed into a single crystal toward the film 9 from the layer 2 through heating, thus forming a lateral epitaxial layer 10. A base layer 3 and an emitter layer 4 are grown, and electrodes 6-8 are formed.

39. 发明专利

JPS62136077A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62136077A
公开(公告)日：1987-06-19
申请号：JP27836785
申请日：1985-12-10
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L29/78
摘要： PURPOSE:To facilitate a super high speed operation by a method wherein a channel region containing a one conductivity type high concentration impurity is formed on a substrate and a source region and a drain region which contain an opposite conductivity type impurity are formed on both sides of the channel region. CONSTITUTION:A channel region 9 is deposited on the surface of a P-type semiconductor substrate 1 made of Si to the thickness of about 200Angstrom by molecular beam epitaxial growth. Then the surface is subjected to hot oxidation to form a gate electrode 6 with the thickness of about 100Angstrom and polycrystalline silicon is deposited on its by vapor phase deposition and patterned to form a gate electrode 7. Then As ions are implanted into the P-type semiconductor substrate 1 by using the gate electrode 7 as a mask and a source region 2 and a drain region 4 are formed by annealing. After that, an SiO2 film is deposited by vapor phase deposition as a protective film and contact holes for the source region, the drain region and the gate electrode are formed in the protective film and Al is deposited and formed into respective electrode shapes.

40. 发明专利

JPS62122177A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62122177A
公开(公告)日：1987-06-03
申请号：JP25969085
申请日：1985-11-21
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778 , H01L29/80
摘要： PURPOSE:To enable a semiconductor device to be operated at ultra high speed by a method wherein a source electrode and a drain electrode respectively in ohmic contact with a source region and a drain region are provided. CONSTITUTION:An undoped GaAs around 5,000Angstrom as a first semiconductor layer 2 as well as a P -Al0.5Ga0.5As around 200Angstrom as a carrier feed layer 3 are deposited on the surface of Cr-GaAs substrate 1 by molecular beam epitaxial process. Then W is evaporated on the carrier feed layer 3 to be formed into a gate electrode 5. Next the substrate 1 is implanted with Si ion using the gate electrode 5 as a mask and then annealed to form a source region 11 and a drain region 12. Later contact holes are made in the carrier feed layer 3 on the source and drain regions 11, 12 to evaporate AuGe/Au completely forming a source electrode 6 and a drain electrode 7. Such a structure fit for integration provided with excellent load driving capacity can be recommended for a device subject to high integration and ultra high speed.

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