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31. 发明专利

JP2001308610A MICROSTRIP LINE, METHOD OF PRODUCING SAME, INDUCTOR ELEMENT AND HIGH FREQUENCY SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001308610A
公开(公告)日：2001-11-02
申请号：JP2000119604
申请日：2000-04-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE MITSURU
IPC分类号： H01F17/02 , H01G4/35 , H01G4/40 , H01L21/338 , H01L27/095 , H01L29/812 , H01P3/08
摘要： PROBLEM TO BE SOLVED: To prevent the increase of the conductor loss even if the width of a microstrip line is reduced. SOLUTION: An earth electrode 12, dielectric layers 13 consisting of strontium titanate of about 0.5 μm in thickness and the microstrip line consisting of linear conductive layers 14 are formed on the boards 11 consisting of semi-insulating GaAs. Linear conductive layers 14 comprises a narrow part 14a of about 0.05 μm in width and a wide part 14b of about 0.5 μm. This linear conductive layer 14 is a laminate consisting of different materials, and it is built by a first layer 15 consisting of tungsten nitride silicon of about 0.1 μm in thickness that is sequentially formed from the board 11 side, a second layer 16 comprising a laminate consisting of Ti of about 0.05 μm in thickness and Au of about 0.5 μm in thickness, and a third layer 17 of Au of about 3 μm in thickness.

32. 发明专利

JPH11150129A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH11150129A
公开(公告)日：1999-06-02
申请号：JP23248198
申请日：1998-08-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ANDA YOSHIHARU , MATSUNO TOSHINOBU , YANAGIHARA MANABU , TANABE MITSURU , MATSUI TOSHIAKI , HIROSE NOBUMITSU
IPC分类号： G03F7/26 , H01L21/027 , H01L21/338 , H01L29/41 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To obtain a good forward taper at the leg of a gate electrode such that the diameter is increased at the top side part, while high throughput and high stability are attained when a T-type gate electrode having a top part and a leg part extending downward therefrom is formed. SOLUTION: A resist film 35 with about 200 nm thickness of PMMA (polymethyl methoacrylate) for EB(electron beam) exposure is applied on a substrate 21, and an upper layer resist film 36 for i-line exposure is applied onto the lower layer resist film 35. A mixing layer 37 of both resist films is then formed on the interface between the upper and lower resist films 36, 35, The upper layer resist film 36 is then developed by the i-line exposure, except for the region 36a for forming the top part to obtain an upper layer opening 36b. Furthermore, the mixing layer 37 and the leg part forming region 35a of the layer resist film 35 are developed through EB exposure to obtain a lower opening 35b having a forward taper.

33. 发明专利

JPH07183315A SEMICONDUCTOR DEVICE AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07183315A
公开(公告)日：1995-07-21
申请号：JP34778393
申请日：1993-12-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU , MASATO HIROYUKI , INOUE KAORU , TANABE MITSURU , NISHII KATSUNORI , TAMURA AKIYOSHI
IPC分类号： H01L21/28 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/812
摘要： PURPOSE:To prevent the deterioration in the reliability and lowering of the high-speed operating properties of a semiconductor device resulting from the disconnection of a T type gate having fine gate length and the increase in the electric resistance. CONSTITUTION:When a gate opening section 10 is formed to an Si3N4 film 3 as an insulating film while using an Al film 5 with an opening section 9 having fine size as a mask, the upper section of the Si3N4 film 3 is removed through isotropic etching, and an opening wider than the mask opening section 9 is formed. The lower section of the Si3N4 film 3 is removed through anisotropic etching. Consequently, the gate opening secion 10 having an inclination in the upward opened direction in approximately the same size as the mask opening section 9 at a lower end section is shaped. A gate metal is deposited, and an approximately Y-shaped gate electrode 7 is formed. Accordingly, the closing of the upper edge of the gate opening section 10 by the gate metal and the extreme reduction of size in the lateral direction of the deposited gate electrode 7 are prevented, and gate length is formed in fine size, thus obtaining high reliability and high-speed operating properties.

34. 发明专利

JP2006325115A TRANSMITTER 审中-公开
公开(公告)号：JP2006325115A
公开(公告)日：2006-11-30
申请号：JP2005148291
申请日：2005-05-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： AKIZUKI TAIJI , TANABE MITSURU
IPC分类号： H04B1/04 , H03F1/32 , H04J11/00
摘要： PROBLEM TO BE SOLVED: To provide a transmitter of an EER method with a high efficiency which does not generate a distortion in an output modulation waveform. SOLUTION: A transmitter of an EER method separates a modulation signal into an amplitude component and a phase component, and inputs the components from a high frequency input terminal and a power voltage terminal of a high frequency power amplifier 110. A delay time correction means 104 is provided which can correct a delay time so that the phase component synthesized by amplifiers 108 and 109 of equal to or more than two stages of the high frequency power amplifier 110, and the amplitude component may be optimally synthesized respectively. As a result, a synthesizing error is reduced at the amplifiers 108 and 109 at each stage, and a distortion component of an output waveform is reduced. COPYRIGHT: (C)2007,JPO&INPIT

35. 发明专利

JP2006086857A Phase-shifting device 审中-公开
标题翻译：相移装置
公开(公告)号：JP2006086857A
公开(公告)日：2006-03-30
申请号：JP2004270041
申请日：2004-09-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TANAKA TAKATOSHI , TANABE MITSURU , KATAOKA SHIGERU
IPC分类号： H03H11/22 , H03H7/20 , H03H7/21
CPC分类号： H03L7/0812 , H03H7/20 , H03H11/20 , H03K2005/00286
摘要： PROBLEM TO BE SOLVED: To provide a 90° phase-shifting device which realizes accurate orthogonal signals or a 90° phase difference and an identical amplitude with high accuracy. SOLUTION: The 90° phase-shifting device is equipped with a signal source 11, a variable-phase shifter 21 which can be varied in phase-shifting rotation through phase-shifting control signals 51, two-multiplication circuits 31 and 32, and a 90° phase comparator 41. The signal source 11 is connected in common to the inputs of the variable-phase shifter 21 and the two-multiplication circuit 32, the output of the variable-phase shifter 21 is connected to the input of the two-multiplication circuit 31, provided that the output of the two-multiplication circuit 31 is represented by a first output signal Q1, and that the output of the two-multiplication circuit 32 is represented by a second output signal I2, the first output signal Q1 and the second output signal I2 are inputted into the 90° phase comparator 41, and the variable-phase shifter 21 can be changed in phase-shifting rotation by phase-shifting control signals 51 as a phase comparison output. By this setup, an accurate 90° phase difference can be realized. An identical amplitude can be realized by the preparation of a correction circuit. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种90°相移装置，其实现精确的正交信号或90°相位差和相同幅度的高精度。解决方案：90°移相装置配备有信号源11，可移相器21，其可以通过相移控制信号51，双倍乘法电路31和32在相移旋转中变化和90°相位比较器41.信号源11共同连接到可变移相器21和双乘法电路32的输入端，可变移相器21的输出端连接到双乘电路31，如果双乘电路31的输出由第一输出信号Q1表示，并且双乘法电路32的输出由第二输出信号I2表示，则第一输出信号Q1和第二输出信号I2被输入到90°相位比较器41中，并且通过相移控制信号51作为相位比较输出，可以将可变移相器21改变为相移旋转。通过这种设置，可以实现精确的90°相位差。通过准备校正电路可以实现相同的幅度。版权所有（C）2006，JPO＆NCIPI

36. 发明专利

JP2001068906A HIGH FREQUENCY DEVICE 失效
公开(公告)号：JP2001068906A
公开(公告)日：2001-03-16
申请号：JP24227999
申请日：1999-08-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE MITSURU , NISHITSUJI MITSURU , ANDA YOSHIHARU
IPC分类号： H01L21/822 , H01L27/04 , H01P3/00 , H01P3/02 , H01P5/02 , H01P11/00
摘要： PROBLEM TO BE SOLVED: To suppress the influence of a parasitic impedance component and to provide an impedance conversion with a little deviation of a load impedance by providing a uniplanar transmission line across adjacent areas on a dielectric substrate. SOLUTION: Concerning a high frequency device 100, an SrTiO3 film 102 of a prescribed size and pattern is formed on a semi-insulating GaAs substrate 101. Thus, the high frequency device 100 is provided with a first region 103, where the SrTiO3 film 102 is formed, and second regions 104 and 114 where the peripheral GaAs substrate 101 is exposed. Further, a coplanar transmission line (CPW) 106 as a uniplanar transmission line, is provided across the first region 103 and the second areas 104 and 114. The SrTiO3 film 102 is provided only at one part (the first region 103) on the surface of the GaAs substrate 101 and the value of a dielectric constant, which the CPW feels equivalent, is made different between the first region 103 and the second region 104.

37. 发明专利

JPH10247727A FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH10247727A
公开(公告)日：1998-09-14
申请号：JP5061897
申请日：1997-03-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE MITSURU
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/15 , H01L29/205 , H01L29/778
摘要： PROBLEM TO BE SOLVED: To provide a field effect transistor which is free from a kink phenomenon. SOLUTION: An undoped In0.52 Al0.48 As first buffer layer 12, a second buffer layer 13 of super lattice structure composed of undoped In0.52 Al0.48 As and undoped Al0.25 Ga0.75 As, an undoped In0.52 Al0.48 As third buffer layer 14, an undoped In0.53 Al0.47 As channel layer 15, an undoped In0.52 Al0.48 As spacer layer 16, a silicon delta doped layer 17, an undoped In0.52 Al0.48 As Schottky layer 18 are successively laminated on an iron-doped semi-insulating InP substrate 11. A cap layer 19 possessed of a recess is formed on the Schottky layer 18. A source electrode 20 and a drain electrode 21 are formed on the cap layer 19, and a gate electrode 22 is provided to the recess.

38. 发明专利

JPH0897235A FORMING METHOD OF GATE ELECTRODE AND MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0897235A
公开(公告)日：1996-04-12
申请号：JP22961394
申请日：1994-09-26
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TANABE MITSURU
IPC分类号： H01L21/28 , H01L21/027 , H01L21/205 , H01L21/338 , H01L29/812
摘要： PURPOSE: To provide a method for forming a gate electrode of small gate length by using lithography. CONSTITUTION: After an SiO2 film 12 is deposited on a GaAs substrate 11, a resist pattern 13 is formed on the SiO2 film 12 which pattern has two oblong apertures formed at an interval of 0.5μm. The resist pattern 13 is used as a mask, and an aperture 14 is formed by etching the SiO2 film 12. After a pair of GaAs layers 15 having mushroom-shaped sections are epitaxially grown at an interval of 0.1μm on the GaAs substrate 11, the SiO2 film 12 is eliminated. A gate electrode whose gate length is 0.1μm is formed by evaporating metal for a gate electrode on the GaAs substrate 11, from the part between the GaAs layers.

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