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31. 发明专利

JP2002176141A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND IC TAG 失效
公开(公告)号：JP2002176141A
公开(公告)日：2002-06-21
申请号：JP2000372727
申请日：2000-12-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , HITACHI COMMUNICATION SYSTEM
发明人： WATANABE KAZUKI , USAMI MITSUO , YAMAMOTO MOROHISA , HAMAGISHI TAKAHIRO
IPC分类号： G06K19/07 , G06K19/077 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To solve the problem where power loss due to a parasitic diode is large and forming efficiency of a power source voltage is low when a voltage doubler rectifier circuit for forming a power source voltage of a semiconductor integrated circuit device mounted on an IC tag is formed on the same silicon wafer. SOLUTION: In a MOS transistor M11, a gate is connected with one terminal LA out of a pair of antenna terminals formed on a semiconductor integrated circuit device. In a MOS transistor M12, a gate is connected with the other terminal LB. A circuit having constitution wherein the respective drains and bulks of the MOS transistors M11 and M12 are connected with ground, a source of the MOS transistor M11 is connected with the antenna terminal LB, and a source of the MOS transistor M12 is connected with the antenna terminal LA, i.e., a circuit for forming reference potential by which operation of a parasitic diode is prevented is arranged between input terminals 1A, 1B of the voltage doubler rectifier circuit CP01. Thereby power loss due to the parasitic diode is reduced.

32. 发明专利

JP2002152080A TAG AND SEMICONDUCTOR INTEGRATED CIRCUIT USED FOR THE SAME 失效
公开(公告)号：JP2002152080A
公开(公告)日：2002-05-24
申请号：JP2000345456
申请日：2000-11-08
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM , HITACHI ULSI SYS CO LTD
发明人： USAMI MITSUO , HAMAGISHI TAKAHIRO , YAMAMOTO MOROHISA , WATANABE KAZUKI , OKUMA TOSHIAKI
IPC分类号： H04B1/59
摘要： PROBLEM TO BE SOLVED: To achieve a prescribed circuit function for realizing an electronic ID authentication tag in a semiconductor chip and to insert the semiconductor chip into a bendable material such as paper as the tag. SOLUTION: In forming the semiconductor chip, a rectifying circuit for circuit driving power voltage generation is constituted of a MOS diode rectifying circuit with capacity coupling MOS diode clamping circuit by using a standard CMOS process. The input terminal of a clock demodulation circuit whose circuit system is similar to the rectifying circuit and whose circuit constant is set in proportion to a load current ratio and that of the rectifying circuit are made to the similar. Thus, the output characteristic of the clock demodulation circuit is made stable with respect to the fluctuation of an input signal level. Then, modulation load current proportional to rectifying voltage is generated and a stable modulation operation is performed by constituting a data transmission modulation circuit by using a MOS transistor whose type is similar to that used for the rectifying circuit for power generation for the data transmission modulation circuit.

33. 发明专利

JP2001274339A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND NONCONTACT TYPE ELECTRONIC DEVICE 失效
公开(公告)号：JP2001274339A
公开(公告)日：2001-10-05
申请号：JP2000088800
申请日：2000-03-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： WATANABE KAZUKI , YOSHINO RYOZO , YAMAMOTO MOROHISA , KINOTA HAJIME , KAMEI KEIJI
IPC分类号： G05F1/56 , G06K19/07 , H01L21/822 , H01L27/04 , H02M7/12 , H04B5/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and a noncontact type electronic device provided with a power circuit realizing formation of stable smoothing voltage with high efficiency and a stable behavior of the internal circuit. SOLUTION: Alternative voltage is applied to the first and the second input terminals, a drain (or a collector) is connected to the second input terminal, rectified current is applied between the first and the second input terminals by a rectifier transistor to which a gate (or a base) and a drain (or a collector) are connected through a resisting means, control voltage is formed so that the rectified voltage gained on the source (or emitter) side of the first rectifier transistor by the first voltage detecting means is matched to the predetermined reference voltage, and the current corresponding to the control voltage is formed by the first voltage control current source to apply the first resisting means. A power circuit so described is mounted on a noncontact type electronic device.

34. 发明专利

JPH06165219A COLOR VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH06165219A
公开(公告)日：1994-06-10
申请号：JP30731292
申请日：1992-11-17
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： KITADE TAKESHI , HOSHINO MASAKAZU , YAMAMOTO MOROHISA , WATANABE KATSUYUKI
IPC分类号： H04N5/95 , H04N9/87
摘要： PURPOSE:To integrate a skew detecting circuit for the skew correction of a reproduction video signal and a reference signal preparing circuit by unnecessitating an outside pin and an outside adjustment. CONSTITUTION:A continuous wave signal SC1 generated by the APC circuit 20 of a reproduction color signal processing circuit 14 is frequency-divided by a 20 frequency-dividing circuit 29, and the continuous wave signal SC2 of a frequency 2fH two times as long as a horizontal synchronizing signal and a window signal WD are prepared. The continuous wave signal SC2 is frequency-divided by a two frequency-dividing circuit 30, and the continuous reference signal Ref of a horizontal synchronizing signal frequency fH is prepared. Also, a horizontal synchronizing signal HS1 separated by the synchronous signal separator circuit 12 of a reproduction luminance signal processing circuit 5 is noise-removed, phase-compared with the window signal WD by an synchronization detecting circuit 31, a reset pulse RS1 is generated when a phase difference is more than a prescribed value, and the 20 frequency-dividing circuit 29 is reset. The phase change due to the skew of the horizontal synchronizing signal HS1 is detected by a flip flop 33 based on the reference signal Ref.

35. 发明专利

JPH04124990A FREQUENCY SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH04124990A
公开(公告)日：1992-04-24
申请号：JP24464990
申请日：1990-09-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO
IPC分类号： H04N9/83 , H04N9/84
摘要： PURPOSE:To prevent the generation of higher harmonic components of 40.1/8XfN and to unnecessitate a frequency conversion circuit by forming the frequency of 2N times (N is a positive integer) of a carrier signal frequency fc with the use of a voltage control type oscillation circuit and synchronizing it with a horizontal synchronizing signal with the aid of a PLL loop. CONSTITUTION:A color sub-carrier signal fsc formed by a crystal oscillation circuit is supplied to a phase shift circuit, and eight signals with different phases by pi/4 are formed here. One of the eight signals is chosen by a changeover circuit and supplied to a flip-flop circuit DFF. The changeover circuit selects a signal with the advanced phase over eight times by pi/4 for one in a ratio of one to one horizontal period other than the sampling period of a horizontal synchronizing signal fN by a changeover signal formed by a changeover signal generation circuit. Thus, the frequency of 40.1/8 is equivalently performed by forty-times of counting operation. Thus, 8/321 frequency can be performed against the eight horizontal synchronizing signals fN.

36. 发明专利

JPS61242109A WAVEFORM SHAPING CIRCUIT 失效
公开(公告)号：JPS61242109A
公开(公告)日：1986-10-28
申请号：JP8250385
申请日：1985-04-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAGISHI HIROAKI , YAMAMOTO MOROHISA
IPC分类号： H03K5/08 , H03K5/01
摘要： PURPOSE:To convert a waveform shaping circuit into an integrated circuit IC by comparing the reference voltage with an input signal and turning on and off the 1st and 2nd transistors to obtain the pulse type signals. CONSTITUTION:When the voltage level of an input signal Vin is reduced less than (Vref+VbeQ1), a transistor TR Q1 is turned off. Then the bias voltage is supplied to a TR Q2 when the voltage level of the signal Vin is less than (Vref-VbeQ1) and turned on. Thus a current I2 flows from a power supply Vcc via a resistance R2 and the TR Q3 and Q2 and serves as the reference current of a current mirror circuit. Then an output current I3 flows to a resistance R4, a TR Q4 and a resistance R5 for production of an output signal Vb of a high level. While the output signal V0' of an inverter 1 is set at a low level. At the same time, an output signal Va is set at a low level and the output signal V0 of an inverter 2 is set at a high level. Thus a waveform shaping circuit can be easily converted into an IC.

37. 发明专利

JPS60103823A FREQUENCY-VOLTAGE CONVERTING CIRCUIT AND CONTROL CIRCUIT USING IT 失效
公开(公告)号：JPS60103823A
公开(公告)日：1985-06-08
申请号：JP21094883
申请日：1983-11-11
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO
IPC分类号： H02P29/00 , H03K9/06
摘要： PURPOSE:To attain accurate F-V conversion independently of temperature dependancy and power supply voltage dependancy and also with simple circuit constitution by designing the circuit that the charging current and the discharge current of a single capacitor obtaining an output voltage of F-V conversion are switched selectively by a switch circuit. CONSTITUTION:A switch SW1 is swtiched on in driving the F-V converting circuit. A switch SW2 is used to select charge/discharge to a capacitor C1. When the switch SW1 is switched on and the switch SW2 is thrown to the position of a fixed contact (a) as shown in the figure, the capacitor C1 is charged via a constant current circuit CS1. When the switch SW1 is turned on and the switch SW2 is thrown to the position of a fixed contact (b) as shown in the figure the capacitor C1 is discharged via a constant current circuit CS2. An example of execution as shown in the figure indicates an example that the F-V converting circuit is applied to a motor control circuit.

38. 发明专利

JPS5979689A Reproducing device of magnetic video signal 失效
标题翻译：重现磁信号的设备
公开(公告)号：JPS5979689A
公开(公告)日：1984-05-08
申请号：JP18909982
申请日：1982-10-29
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO
IPC分类号： H04N9/84 , H04N5/93 , H04N5/932
CPC分类号： H04N5/932
摘要： PURPOSE:To prevent the generation of a flicker phenomenon due to skew distortion by compensating the pulse width varied by the skew distortion. CONSTITUTION:If the 4th pulse of a horizontal synchronizing signal appears faster by the skew distortion, an edge pulse generating circuit 35 generates an edge pulse P5 to reset a pulse generating circuit 31 at the switching of a channel. Consequently, the pulse width t1 of a pulse P3 is synchronized with a pulse P5 and turned to an L level and the pulse width t1 is turned to t1''. Since a pulse P1 resets also a counter 32, no counted output is obtained from the counter 32. On the other hand, the pulse generating circuit 31 is actuated again by the 4th pulse of a horizontal synchronizing signal and the H level part with the time width t1 corresponding to the 4 pulses of the horizontal synchronizing signal appears in the pulse P3 again. Therefore, an upper flicker due to the skew distortion does not appear in a reproduced picture.
摘要翻译：目的：通过补偿由偏斜失真变化的脉冲宽度来防止由于偏斜失真而产生闪烁现象。构成：如果水平同步信号的第4脉冲通过偏斜失真出现得更快，则边沿脉冲发生电路35产生边沿脉冲P5，以在通道切换时复位脉冲发生电路31。因此，脉冲P3的脉冲宽度t1与脉冲P5同步，变为L电平，脉冲宽度t1变为t1“。由于脉冲P1也复位计数器32，所以不能从计数器32获得计数的输出。另一方面，脉冲发生电路31再次由水平同步信号的第四脉冲和具有时间的H电平部分对应于水平同步信号的4个脉冲的宽度t1再次出现在脉冲P3中。因此，由于偏斜失真引起的上部闪烁不会出现在再现的图像中。

39. 发明专利

JP2001297979A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001297979A
公开(公告)日：2001-10-26
申请号：JP2000121064
申请日：2000-04-17
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： USAMI MITSUO , OKI MASARU , YAMAMOTO MOROHISA
IPC分类号： H01L21/822 , H01L21/027 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of a wafer following diameter increase of the semiconductor wafer. SOLUTION: A first chip region is formed on a semiconductor wafer. Second chips are placed in a region between the region for the first chips and the outermost periphery of the semiconductor wafer where the first chip can not be formed.

40. 发明专利

JP2001060868A AMPLIFIER CIRCUIT, LC RESONANCE CIRCUIT, VOLTAGE CONTROL OSCILLATION CIRCUIT, PLL CIRCUIT, VIDEO SIGNAL PROCESSING CIRCUIT AND VIDEO TAPE RECORDER 失效
公开(公告)号：JP2001060868A
公开(公告)日：2001-03-06
申请号：JP23298299
申请日：1999-08-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NACHI SHIKIKO , YAMAMOTO MOROHISA , KAWABATA SUMI
IPC分类号： H03B5/12 , H03F3/343 , H03L7/099 , H04N5/445
摘要： PROBLEM TO BE SOLVED: To obtain a PLL circuit by which a stable synchronization signal is generated through the use of an LC resonance type VCO by providing the phase shift circuits of a phase in the oscillation output of an LC resonance circuit, feeding-back the signal to a voltage-current converting means and obtaining the oscillation output of a desired frequency. SOLUTION: In an LC resonance type VCO circuit 601 constituting the PLL circuit, an LC circuit 303 is connected to the output terminal of an amplifier circuit 304 and the output terminal of an oscillation reference bias power source circuit 301 to constitute an LC resonance circuit. The phase shift circuits 306 and 307 feed back a phase shift advance signal FORWARD and a phase delay signal DELAY to the amplifier circuit 304, they are added and amplified and the output signal AFCOSC of the LC resonance circuit is obtained. Differential control voltages VCP and VCM are generated from a control voltage VLPF in a level shift circuit 302 and a rate for adding and amplifying the phase advance signal FORWARD and the phase delay signal DELAY in the amplifier circuit 304 is variably controlled.

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