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31. 发明专利

JPH11214623A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11214623A
公开(公告)日：1999-08-06
申请号：JP2780298
申请日：1998-01-26
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWAI YOZO , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , SHINAGAWA YUTAKA
IPC分类号： H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To realize a stable operation with low power consumption by combining delay circuits operating with constant voltage irrespective of power voltage from an outer terminal, generating the timing signal of a level corresponding to power voltage and controlling an inner circuit. SOLUTION: Delay circuits DL1-3 constituting a first timing generation circuit are operated by inner clamping voltage obtained by dropping power voltage to about 2.5 V so that the delay time of the operation voltage is not affected by power voltage supplied from an outer terminal, the fluctuation of 2.7-3.6 V, for example. Level conversion circuits LOGC1&LVC-LOGC3&LVC provided with logic functions constituting a second timing generation circuit to which the input N1 and the delay signals N2-N4 of the respective delay circuits DL1-3 are transmitted convert levels corresponding to signal levels corresponding to precharge/sense amplifier/discharge circuits which correspond to precharge/ sense amplifier/discharge operations and operate with power voltage and they form timing signals CT1-3.

32. 发明专利

JPH11185489A SEMICONDUCTOR STORAGE AND DATA PROCESSOR 失效
公开(公告)号：JPH11185489A
公开(公告)日：1999-07-09
申请号：JP35461497
申请日：1997-12-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , KAWAI YOZO , MISHINA DAISUKE , SHINAGAWA YUTAKA , TANAKA TOSHIHIRO , MATSUBARA KIYOSHI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To quicken memory access. SOLUTION: A semiconductor storage containing a plurality of word lines and a memory cell connected to them is provided with a first driver circuit (DPE) that is formed by a transistor having a high breakdown voltage and selectively drives a corresponding word line to write data to the memory cell, and a second driver circuit (DR) that is formed by a transistor with higher driving capability than a transistor constituting a high breakdown voltage driver and selectively drives the word line to read the data from the memory cell, thus speeding up word line selection when reading data.

33. 发明专利

JPH02248071A OSCILLATION CIRCUIT 失效
公开(公告)号：JPH02248071A
公开(公告)日：1990-10-03
申请号：JP6772389
申请日：1989-03-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SUZUKAWA KAZUFUMI , SHIMIZU TAKAYOSHI
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L27/118 , H03B5/36
摘要： PURPOSE:To reduce noises so as to improve an oscillation circuit in reliability by a method wherein a gate formed of a CMOS is provided between two MOSs in an oscillation circuit in which a feedback resistor is realized through resistance between the drain and the source of a PMOS and an NMOS. CONSTITUTION:As shown in a figure, a PMOS (gate 3a, diffusion layer 2c), a CMOS (gate 3a, diffusion layers 2a and 2b), and an NMOS (gate 3a, diffusion layer 2d) are successively arranged from top to bottom, and wirings 5a (l1) and 5b (l2), which connect them, are arranged in parallel in a longitudinal direction. By this arrangement, the of the wirings 5a and 5b can be made nearly linear and minimized in length, so that noises are prevented from occurring due to wiring made large in length. The wirings 5a and 5b can be made equal in length (l1=l2), so that noises caused by the length difference between wirings can be prevented, and moreover the wiring 5a can be made separate from the wiring 5b by the length of the gate 3a. wherefore crosstalk noises are restrained. By this constitution, an oscillation circuit of this design can be improved in reliability.

34. 发明专利

JPS5897186A MAGNETIC BUBBLE MEMORY DRIVING CIRCUIT 失效
公开(公告)号：JPS5897186A
公开(公告)日：1983-06-09
申请号：JP19293781
申请日：1981-12-02
申请人： HITACHI LTD
发明人： ISHIDA KAZUHIRO , SUZUKAWA KAZUFUMI
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To generate a magnetic bubble generating pulse having faster leading time and slow trailing time easily and surely, by delaying only the off-time of a transistor (TR) forming a trapezoidal wave with a diode, resistor and a capacitor, etc. CONSTITUTION:Bias split resistors R1, R2 of a TR2 for driving and a TR1 for pre-driving generate pre-driving pulse and only the off-time of the TR2 is delayed with a diode 4, a resistor R4 and a capacitor C which disconnect the resistors R1, R2 from the base for the trailing time. Thus, drive pulses which have faster leading time and slow trailing time are generated easily and surely, allowing to improve the magnetic bubble write characteristics via a generator 3 and to attain a magnetic bubble memory driving circuit with high quality and reliability without generation of a write error.

35. 发明专利

JP2002109894A NONVOLATILE MEMORY, SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME INSIDE, AND WRITING METHOD FOR NONVOLATILE MEMORY 失效
公开(公告)号：JP2002109894A
公开(公告)日：2002-04-12
申请号：JP2000302696
申请日：2000-10-02
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , YAMAKI TAKASHI , MAKUTA KIICHI , WADA MASASHI , KAWAJIRI YOSHIKI
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12
摘要： PROBLEM TO BE SOLVED: To solve the problem of a nonvolatile memory that a conventional writing system which shifts writing timing, bit by bit, wastes a time since writing operation corresponding to write data is not performed and further can not perform stable writing operation since the voltage generated by an internal boosting circuit is easy to vary because of large variation in write current depending upon the pattern of the write data. SOLUTION: The nonvolatile memory like a flash memory decides data in writing operation to skip the writing of bits being logic '1' (or logic '0') of the write data and successively write bits of logic '0' (or logic '1').

36. 发明专利

JP2001176279A SEMICONDUCTOR CIRCUIT DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001176279A
公开(公告)日：2001-06-29
申请号：JP35486199
申请日：1999-12-14
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To reduce the potential variation dependence of power source voltage of negative boosting voltage. SOLUTION: A negative boosting voltage generating circuit is constituted of a charge-pump circuit, a clock generating circuit supplying a clock signal to the charge pump circuit, and a voltage comparing circuit comparing divided voltage from a first resistor voltage-dividing potential difference between the output voltage of the charge pump circuit the output of a reference voltage generation circuit, and divided voltage from a second resistor voltage-dividing power source voltage, and controlling clock supply operation from a clock supply circuit to the charge pump circuit based on boosting voltage formed by the charge pump circuit.

37. 发明专利

JP2000090675A NON-VOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING BUILT-IN NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000090675A
公开(公告)日：2000-03-31
申请号：JP25264898
申请日：1998-09-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SHINAGAWA YUTAKA , FUJITO MASAMICHI , SUZUKAWA KAZUFUMI , KAWAI YOZO , TANAKA TOSHIHIRO , YADA NAOKI
IPC分类号： G11C11/41 , G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To shorten a write time required by decreasing the total number of write by deciding the completion of write by read at voltage, where the conditions of verification are relaxed in response to the number of the application of write voltage to the same storage element. SOLUTION: A circuit capable of generating verify voltage set at a slightly high level while imparting an allowance value to verify voltage at a preset specified level besides the verify voltage at the preset specified level as write verify voltage applied to a word line and a circuit capable of changing over these voltage are mounted on a flash memory. A counter counting the number of the application of write pulses is prepared in a memory for operation. A maximally small value within a range that a malfunction by the noises of a sense amplifier can be avoided is used as the allowance value of verify voltage. Verify voltage after the application of the odd number of write pulses is made higher than that after the application of the even number of write pulses.

38. 发明专利

JP2000083069A DIGITAL SIGNAL TRANSMISSION CIRCUIT OF SEMICONDUCTOR DEVICE, SMALL SIGNAL SENSE CIRCUIT AND SEMICONDUCTOR DEVICE USING DIGITAL SIGNAL TRANSMISSION CIRCUIT OR SMALL SIGNAL SENSE CIRCUIT 失效
公开(公告)号：JP2000083069A
公开(公告)日：2000-03-21
申请号：JP13345599
申请日：1999-05-14
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , NAKAGOME YOSHINOBU , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI
IPC分类号： G11C11/417 , G11C11/409 , H03K19/0175 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that realizes a signal transmission system whose noise and power consumption alike are small and which is suitable for high speed signal transmission between physically separated blocks or a small sense circuit which is suitable to read memory storage information and is high in speed and highly reliable. SOLUTION: In this signal transmission circuit where a preceding stage logic circuit 10 and an output circuit 20 on a transmitting side and an input circuit 30 and a next stage logic circuit 40 on a receiving side exist on different semiconductor chips or are arranged at separate positions on the same chip and they are connected by a pair of complementary signal lines, digital signal transmission is performed by the complementary signal line pair that symmetrically shifts from almost middle potential between high potential and low potential and the input circuit 30 where one of the complementary signal line pair is connected to the source of a 1st field effect transistor M1T and the gate of a 2nd field effect transistor M1B, the other is connected to the gate of the M1T and the source of the M1B and the drains of the M1T and M1B are connected to a transistor conduction detection circuit 310 is provided.

39. 发明专利

JP2000011663A CONTROL-SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME 失效
公开(公告)号：JP2000011663A
公开(公告)日：2000-01-14
申请号：JP17884698
申请日：1998-06-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： FUJITO MASAMICHI , SUZUKAWA KAZUFUMI , KAWAI YOZO , SHINAGAWA YUTAKA
IPC分类号： G11C11/419 , G06F1/10 , G11C11/407 , G11C11/409 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a control signal-generating circuit capable of generating a control signal which is less affected by conditions such as a temperature, a process, a power supply voltage or the like, and suppressing a control period of a sense amplifier to a certain time period or less even when an operating frequency is lowered, and further provide a semiconductor integrated circuit device utilizing the same which is suitable to be used for controlling a sense amplifier. SOLUTION: A control signal generating circuit for a sense amplifier is composed of a monitoring circuit 1 for forming a clock signal, delay circuits 2 and 3 for delaying an input signal, and a combination logic circuit 4 for generating a clock signal by using the delayed signals. When a frequency of a clock signal CKM is high, a leading edge and a trailing, edge of the clock signal CKM are respectively used, while only the leading edge is used when the frequency is low. Thus, a clock signal CSA having a high period within a predetermined range can be generated without causing the high period of a signal level to become longer.

40. 发明专利

JPH11186503A STEP-UP CIRCUIT, SEMICONDUCTOR STORAGE DEVICE, AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH11186503A
公开(公告)日：1999-07-09
申请号：JP35461297
申请日：1997-12-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： FUJITO MASAMICHI , KAWAI YOZO , SUZUKAWA KAZUFUMI , SHINAGAWA YUTAKA , TANAKA TOSHIHIRO , KUBOTA HIROYUKI
IPC分类号： G11C16/06 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of a step-up circuit which includes a charge pump. SOLUTION: A comparison circuit 50A for comparing the output voltage of a charge pump to a reference voltage, a conversion circuit 40A for level- conversion of comparison result of the comparison circuit, and a counterflow preventive circuit 20A which, based on the output signal of the conversion circuit, blocks a current from counter-flowing into the charge pump, while the charge pump stops are provided. By blocking the counterflow into an output terminal of the charge pump based on the output signal of the conversion circuit 40A, the reduction in power consumption of the step-up circuit which includes the charge pump is attained.

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