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31. 发明专利

JPH10254936A LOGIC OPERATION CONTROL METHOD FOR LOGIC CIRCUIT, METHOD FOR CONTROLLING AND CALCULATING POWER CONSUMPTION OF SEMICONDUCTOR LOGIC CIRCUIT AND SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JPH10254936A
公开(公告)日：1998-09-25
申请号：JP5879397
申请日：1997-03-13
申请人： HITACHI LTD
发明人： SAITO TATSUYA , YAGYU MASAYOSHI , YAMASHITA HIROKI , CHIBA TSUNEYO , YAMAMOTO MASAKAZU
IPC分类号： G01R31/317 , G01R31/28 , G01R31/30 , G01R31/319 , G06F17/50 , H01L21/82 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To test the operation of logic circuit while reflecting the fluctuation of operation rate, namely, power consumption. SOLUTION: Among flip-flop circuits 104, 105, 106 and 107 in flip-flop circuit groups 101 and 102 and a combination circuit group 103, a control signal input terminal Tin is provided in a logic gate circuit 109 having plural input signal terminals A and B and a control signal TEST for test is inputted. When the control signal TEST is at a low level (L), ordinary logic operation is performed but when this signal is at a high level (H), power consumption test operation is performed. Namely, the flip-flop circuits 104 and 105, to which the control signal TEST is inputted, repeat the switching of H and L synchronously with a clock at the outputs of Q1 and Q2 in spite of input signal applied to D1 and D2 and it is transmitted to logic gate circuits 108 and 109 in the combination circuit but the logic gate circuit 109, to which the control signal TEST is inputted, repeats the switching of H and L according to one of input signals without performing any logic operation.

32. 发明专利

JPH10126453A INTERFACE CIRCUIT 失效
公开(公告)号：JPH10126453A
公开(公告)日：1998-05-15
申请号：JP27202496
申请日：1996-10-15
申请人： HITACHI LTD
发明人： SAITO TATSUYA , KATO TAKESHI , YAGYU MASAYOSHI , IWANAGA TOMOHISA , YAMASHITA HIROKI , NAKANISHI KEIICHIRO
IPC分类号： G06F3/00 , H04L7/00 , H04L25/08 , H04L25/40
摘要： PROBLEM TO BE SOLVED: To reduce an error due to steady/non-steady noise and environmental fluctuation. SOLUTION: Data in n-bit and redundant information in m-bit to discriminate an error are fed to a receiver circuit 102, in which they are fed respectively to k-set of FFs 104 (n, m, k are natural numbers and k>=2). Outputs from the FFs 104 k-sets in (n+m)-bit are fed to k-sets of error detection circuits 105 and (n+m)-sets of majority decision circuits 106. Outputs of the error detection circuits 105 are fed to a phase change circuit 107. Outputs of the majority decision circuits 106 are outputs of the receiver circuit 102. The phase change circuit 107 receives a signal TEST and a clock signal CLOCK and provides outputs of k-sets of clock signals CLOCK1-CLOCKk whose phases differ from each other. A discrimination circuit 108 discriminates it that no error is in existence based on outputs from the error detection circuits 105 and the phase change circuit 107.

33. 发明专利

JPH06169060A ELECTRONIC CIRCUIT DEVICE 失效
公开(公告)号：JPH06169060A
公开(公告)日：1994-06-14
申请号：JP22169893
申请日：1993-09-07
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , ITOU HIROYUKI , NAKANISHI KEIICHIRO , SAITO TATSUYA , KOBAYASHI TORU , ISOMURA SATORU
IPC分类号： H01L21/822 , H01L27/04
摘要： PURPOSE:To provide a noise decreasing structure for a power-supply wiring system, which decreases the voltage noises generated in the power supply wiring system caused by the current noises when an electronic circuit is operated and blocks the propagation of the voltage noises in an electronic circuit device, wherein the electronic circuits are mounted in a high density. CONSTITUTION:A power supply wiring 101 supplies power to the individual electronic circuit constituting an electronic circuit device. Load circuits 105, 106 and 107 are connected to the power supply wiring 101 within the range, wherein the voltage noises generated in the power supply wiring reach in time that is about one half the pulse width of the noise current when the electronic circuit is operated. These load circuits 105, 106 and 107 are constituted of the series circuits of resistors and capacitors. Therefore, the generated voltage noises can be decreased by the reflected wave, which is generated at the connecting points of the load circuits, and the voltage noises, which are propagating through the power supply wiring, can be attenuated.

34. 发明专利

JPH05242929A 失效
公开(公告)号：JPH05242929A
公开(公告)日：1993-09-21
申请号：JP4094092
申请日：1992-02-27
申请人： HITACHI LTD
发明人： NAKANISHI KEIICHIRO , YAMASHITA HIROKI , SAITO TATSUYA , ITOU HIROYUKI
IPC分类号： H01R13/66 , H01R13/719
摘要： PURPOSE:To enable high-frequency pulses to be transmitted without a change in connector structure, and provide a connector suitable for a large-sized logic device including a computer by inserting a connecting element and a capacitive element between a terminal for signal connection and a terminal for connecting a power supply having ground potential. CONSTITUTION:When a small printed circuit board 1 is connected to a large printed circuit board 3 via a connector 2, a transmission signal from a signal transmission circuit 4 in the board 1 is sent to a signal pin 7 fixed to the lower side of the board 1 via a through-hole 5. The pin 7 is kept in contact with a metal piece 9 having spring characteristics inside the connector 2, and sends the signal to a through-hole 11 in the board 3. In this case, both the signal transmission circuit 4 in the board 1 and a signal transmission circuit 13 in the board 3 are so adjusted to have the impedance of the same characteristics. Also, a power supply hole 6 in the board 1 and a power supply hole 12 in the board 3 are connected to each other via a power supply pin on the lower side of the board l, and a metal piece 10 in the connector 2 for power supply via an IC chip. Furthermore, a characteristic element 15 and a capacitive element 16 are laid between the pins 7 and 8, thereby preventing an echo inside the connector 2.

35. 发明专利

JPH05218815A FLIP-FLOP CIRCUIT 失效
公开(公告)号：JPH05218815A
公开(公告)日：1993-08-27
申请号：JP2110092
申请日：1992-02-06
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , ITOU HIROYUKI , SAITO TATSUYA
IPC分类号： H03K3/286
摘要： PURPOSE:To increase the date fetching speed and also to improve the resistance to the soft errors caused by the alpha rays by controlling the operation of a transistor of a feedback emitter follower part by means of the input of e clock. CONSTITUTION:An ECL order circuit part 119 outputs the value corresponding to the data input D to the nodes A1 and A2 based on the clock input CK. A date holding part 120 holds the value of both nodes A1 and A2 of the circuit 119 regardless of the change of the input CK. An output buffer part 122 outputs the value of the nodes A1 and A2 held by the part 120 as the negative acknowledge side output QB and the acknowledge side output QT respectively. Then a feedback emitter follower part 121 feeds the output of the node A1 of the circuit 119 back to the part 120 via a node A3. Then the input CK is connected to the transistor 111 of the part 121.

36. 发明专利

JPH04186922A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04186922A
公开(公告)日：1992-07-03
申请号：JP31399690
申请日：1990-11-21
申请人： HITACHI LTD
发明人： TANAKA HIRONORI , MASUDA NOBORU , YAMASHITA HIROKI
IPC分类号： H03K19/0952
摘要： PURPOSE:To suppress the potential fluctuation of a common source and to set the falling time of an output signal at a high speed by connecting a capacitance element between the common source for which the source electrode of a switch FET of a current switching part is connected in common, and a constant-voltage power source. CONSTITUTION:To a transistor F201, a current I2 from a transistor FL1 and a discharging current IL from a load capacitance connected to a terminal (a) flow, and a part of I2 and IL is used as the charging current of a capacitor CC. When the value of CC is set in advance to the sufficient large value of about several pFs, a potential difference across CC is hardly varied in a short time when outputs of (a) and (-a) are switched. CC can absorb a current exceeding a current I3 flowing through a transistor F202, and simultaneously, keeps the potential of C constant, and works so that the current exceeding I3 can be allowed to flow to F201.

37. 发明专利

JPH04186919A INTERFACE CIRCUIT 失效
公开(公告)号：JPH04186919A
公开(公告)日：1992-07-03
申请号：JP31399790
申请日：1990-11-21
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , ITOU HIROYUKI , SAITO TATSUYA , NAKANISHI KEIICHIRO
IPC分类号： H03K17/04 , H03K19/018
摘要： PURPOSE:To execute the transmission at high speed without increasing the power consumption by connecting a diode in the forward direction between the base and the emitter of a first NPN transistor. CONSTITUTION:A current signal is transmitted to an emitter ground circuit 115 consisting of a load resistance 106 and an NPN transistor 105, and the diode 114 of an input circuit 102 of receiving side through a signal line. The input impedance of the receiving side comes to a parallel impedance of the base-emitter diode of the transistor 105 and the forward resistance of the diode 114, therefore, comes to a low impedance like AC. Especially, by enlarging the joining area of the diode 114 or the transistor 105, to convert into the lower impedance is made possible, a delay time caused by adding a floating capacity 113 is shortened and the transmission can be executed at a high speed.

38. 发明专利

JPS59221888A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS59221888A
公开(公告)日：1984-12-13
申请号：JP9565383
申请日：1983-06-01
申请人： HITACHI LTD
发明人： HAYASHI TAKEHISA , TANAKA HIRONORI , YAMASHITA HIROKI
IPC分类号： G11C11/417 , G11C11/34
摘要： PURPOSE:To attain high speed operation by using a normally-off type FET for a memory cell and a normally-on type FET for a write circuit so as to improve the driving capability of a write circuit of a semiconductor storage device with a simple constitution and high density. CONSTITUTION:The storage section of the memory cell MC is formed by normally-off type FETs (FEFT) T1-T4, the constitution of the memory cell is simplified and also the semiconductor storage device is formed easily as high density device. On the other hand, normally-on type FETs (DFET) T5, T6 are used for the write circuit thereby increasing the current, and the driving circuit with high driving capability and high speed write is attained. Moreover, in including an EFET and a DFET to a load of a data line and generating a voltage drop by read current and a voltage drop by write current by the EFET and DFET respectively, the effect of variation in the characteristic of a transistor at read/write is reduced.

39. 发明专利

JPS59213195A Connecting device 失效
公开(公告)号：JPS59213195A
公开(公告)日：1984-12-03
申请号：JP8575083
申请日：1983-05-18
申请人： Hitachi Ltd
发明人： YAMASHITA HIROKI , FUKUI MUNETOSHI
IPC分类号： H05K3/32 , B23K1/00 , H05K3/34 , B23K1/02

40. 发明专利

JPS5884445A LARGE SCALED INTEGRATED CIRCUIT 失效
公开(公告)号：JPS5884445A
公开(公告)日：1983-05-20
申请号：JP18226881
申请日：1981-11-16
申请人： HITACHI LTD
发明人： ITOU HIROYUKI , MASAKI AKIRA , YAMASHITA HIROKI , HOSOSAKA HIROSHI
IPC分类号： H01L21/822 , G11C11/411 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H01L27/10 , H01L27/118 , H03K3/2885 , H03K19/173
摘要： PURPOSE:To enhance the free degree of LSI constitution and enhance the integration degree as the rate of utilizing elements or chip areas improves, by completely freely mixing memory parts with logical gate parts resulting in the constitution of a memory logical gate mixed LSI. CONSTITUTION:The connection indicated by full lines in the figure is necessary in common when forming memory cells and logical gates, and the connection by broken lines is the wiring selectively performed according to the formation of the memory cell or the logical gate. The figure 4 represents the connection when constituting the memory cell, and the figure 5 represents the connection when constituting the 4-input OR/NOR ECL (emitter coupled logical) gate. In the figure, intermediate taps are provided on resistors 91, 101, 112 so that the circuit current may be varied according to the case of the memory cell or the logical gate. Resistors 12, 13 of emitter followers are used for the logical gate, and, in the case of memory cell, resistors, 12, 13 are used only in one cell in digit direction for wired OR.

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