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1. 发明专利

JP2008113219A Antenna for rfid tag reader 有权
标题翻译： RFID标签读取器天线
公开(公告)号：JP2008113219A
公开(公告)日：2008-05-15
申请号：JP2006294773
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAMISAKA KOICHI , SHINDO HIDEHIKO , YAMAMOTO MASAKAZU
IPC分类号： H01Q9/16 , G06K19/07 , H04B1/59 , H04B5/02
摘要： PROBLEM TO BE SOLVED: To provide an antenna for an RFID tag reader capable of reading data from a target RFID tag even though a plurality of RFID tags are present adjacently. SOLUTION: The antenna 101 for the RFID tag reader is characterized in that two antenna elements 4a and 4b branched from a feeding point 3 to both sides are arranged facing each other to constitute a dipole antenna. When the wavelength of a radio wave is defined as λ, each electric length from the feeding point 3 to each of end parts of the antenna elements is about λ/4. When one antenna element 4a has a plus potential, the other antenna element 4b has a minus potential and the two antenna elements 4a and 4b each radiate opposite-phase electromagnetic waves. Since energy concentrates in an area S surrounded by the antenna elements 4a and 4b in this way to make the strength of an electromagnetic field the largest at the end parts of the antenna elements 4a and 4b, data is read from an RFID tag present in the area S. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使多个RFID标签相邻存在，也可以提供能够从目标RFID标签读取数据的RFID标签读取器的天线。解决方案：用于RFID标签读取器的天线101的特征在于，从馈电点3分支到两侧的两个天线元件4a和4b彼此相对布置以构成偶极子天线。当无线电波的波长被定义为λ时，从馈电点3到天线元件的每个端部的每个电长度大约为λ/ 4。当一个天线元件4a具有正电位时，另一个天线元件4b具有负电位，并且两个天线元件4a和4b分别辐射反相电磁波。由于能量集中在由天线元件4a和4b围绕的区域S中，以使天线元件4a和4b的端部处的电磁场的强度最大，所以从存在于天线元件4a和4b中的RFID标签读取数据区域S.版权所有（C）2008，JPO＆INPIT

2. 发明专利

JPH10254936A LOGIC OPERATION CONTROL METHOD FOR LOGIC CIRCUIT, METHOD FOR CONTROLLING AND CALCULATING POWER CONSUMPTION OF SEMICONDUCTOR LOGIC CIRCUIT AND SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JPH10254936A
公开(公告)日：1998-09-25
申请号：JP5879397
申请日：1997-03-13
申请人： HITACHI LTD
发明人： SAITO TATSUYA , YAGYU MASAYOSHI , YAMASHITA HIROKI , CHIBA TSUNEYO , YAMAMOTO MASAKAZU
IPC分类号： G01R31/317 , G01R31/28 , G01R31/30 , G01R31/319 , G06F17/50 , H01L21/82 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To test the operation of logic circuit while reflecting the fluctuation of operation rate, namely, power consumption. SOLUTION: Among flip-flop circuits 104, 105, 106 and 107 in flip-flop circuit groups 101 and 102 and a combination circuit group 103, a control signal input terminal Tin is provided in a logic gate circuit 109 having plural input signal terminals A and B and a control signal TEST for test is inputted. When the control signal TEST is at a low level (L), ordinary logic operation is performed but when this signal is at a high level (H), power consumption test operation is performed. Namely, the flip-flop circuits 104 and 105, to which the control signal TEST is inputted, repeat the switching of H and L synchronously with a clock at the outputs of Q1 and Q2 in spite of input signal applied to D1 and D2 and it is transmitted to logic gate circuits 108 and 109 in the combination circuit but the logic gate circuit 109, to which the control signal TEST is inputted, repeats the switching of H and L according to one of input signals without performing any logic operation.

3. 发明专利

JPH09232503A THREE-DIMENSIONAL LAMINATE MODULE 失效
公开(公告)号：JPH09232503A
公开(公告)日：1997-09-05
申请号：JP3332096
申请日：1996-02-21
申请人： HITACHI LTD
发明人： KATO TAKESHI , TOKUDA MASAHIDE , ITOU HIROYUKI , ITABASHI TAKESHI , YOSHIMURA TOYOFUSA , TAKAHASHI AKIO , YAMAMOTO MASAKAZU
IPC分类号： H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a small, thin, multi-pin low cost three-dimensional laminated module by the interlayer connection at high density. SOLUTION: Chips 110 are connected to thin interconnection films 120, these films and thin adhesive films 130 are alternately laminated to directly connect via holes 125 formed through the films 120 to vias 131 formed through the films 130 whereby the via holes can be made fine and at small pitches and hence the inerlayer connection can be made at high density to reduce the module mounting area. Since the number of parts of the module structure is small and lamination process is simple and superior in mass productivity, the cost can be reduced.

4. 发明专利

JPS60247992A INTEGRATED CIRCUIT CHIP MOUNTING SUBSTRATE 失效
公开(公告)号：JPS60247992A
公开(公告)日：1985-12-07
申请号：JP10253984
申请日：1984-05-23
申请人： HITACHI LTD
发明人： NAKANISHI KEIICHIROU , YAMAMOTO MASAKAZU , HIROTA KAZUO
IPC分类号： H05K3/34 , H01L23/32 , H01L23/52 , H05K1/02 , H05K3/32 , H05K3/38 , H05K3/46

5. 发明专利

JPS60140848A MOUNTING DEVICE FOR ELECTRONIC APPARATUS 失效
公开(公告)号：JPS60140848A
公开(公告)日：1985-07-25
申请号：JP24692283
申请日：1983-12-28
申请人： HITACHI LTD
发明人： YAMAMOTO MASAKAZU , HAYASHI TAKEHISA
IPC分类号： H05K7/14 , H01L23/32 , H01L23/538 , H05K1/14
摘要： PURPOSE:To obtain the titled device having a fine, multipin connector in module mounting by utilizing bare chips of semicondutor. CONSTITUTION:Several pieces of wiring substrate (package) 3 loaded with LSI's, resistor chips 2, and the like are stacked, and respective substrates 3 are electrically connected with a wiring substrate (platter) 4. The connection of the package 3 with the platter 4 is made by a connector 10. Semiconductor chips 7 with logical circuits and terminal resistors are mounted to a block 6 installed on the package 3 with solder 5 and to a platter 4, respectively. These chips 7 are electrically connected to the block 6 or the platter 4 by wire bonding 8. For the purpose of connecting the substrates 3 and 4, the connector board 10 having pins 9 is press-welded to the chip 7 and then electrically connected by touching the pads on the chip with the pins 9.

6. 发明专利

JPS60136184A CONNECTOR UNIT 失效
公开(公告)号：JPS60136184A
公开(公告)日：1985-07-19
申请号：JP24202583
申请日：1983-12-23
申请人： HITACHI LTD
发明人： YASUNAGA MORITOSHI , YAMADA MINORU , ASANO MICHIO , KAMIKAWAI RIYOUTAROU , SATOU KAZUO , MASAKI AKIRA , YAMAMOTO MASAKAZU , HIROTA KAZUO
IPC分类号： H01R4/02

7. 发明专利

JPS5998596A MULTILAYER CERAMIC BOARD 失效
公开(公告)号：JPS5998596A
公开(公告)日：1984-06-06
申请号：JP20829882
申请日：1982-11-27
申请人： HITACHI LTD
发明人： YAMAMOTO MASAKAZU , WATANABE YUTAKA
IPC分类号： H05K3/46 , B32B9/00 , B32B15/04

8. 发明专利

JPH10150353A PHASE COMPARATOR CIRCUIT 失效
公开(公告)号：JPH10150353A
公开(公告)日：1998-06-02
申请号：JP22601097
申请日：1997-08-22
申请人： HITACHI LTD
发明人： MASUDA NOBORU , YAMAMOTO MASAKAZU , ITOU HIROYUKI , SAITO TATSUYA
IPC分类号： H03K5/26
摘要： PROBLEM TO BE SOLVED: To raise warning only on the occurrence of a specific phase shift by comparing phases of 1st and 2nd signals and outputting a warning signal when a phase difference reaches a threshold level so as to avoid an error in visual error in the case of using an oscilloscope. SOLUTION: When phases of signals from input terminals 1, 2 are equal to each other, the phase of the signal given to a node 102 of a phase comparator circuit 10 via a circuit 21 is delayed more than that given to a node 101. While a level of a node 107 reaches an intermediate level after the signal passes through the phase comparator, a level of a node 108 goes to a high level, and an output from a differential amplifier 50 goes to a low level. In the case that the signal delivered to the node 102 via a circuit 102 is reverse to the relation above, an output from a differential amplifier 50 goes to a high level, and a warning signal output terminal 4 coupled with the circuit 21 goes to a low level, and then no warning signal is outputted. On the other hand, when the phase of the signal from the input terminal 1 is lagged more than the phase of the signal from the input terminal 2 and the phase difference reaches a dead band difference via the circuit 21, a warning signal is outputted from the output terminal 4.

9. 发明专利

JPH0974352A PLL CIRCUIT AND FREQUENCY COMPARATOR CIRCUIT 失效
公开(公告)号：JPH0974352A
公开(公告)日：1997-03-18
申请号：JP18277396
申请日：1996-06-24
申请人： HITACHI LTD
发明人： MASUDA NOBORU , NAKAJIMA KAZUNORI , FUJITA BUNICHI , YAMAMOTO MASAKAZU , MIZUNO KAZUHIKO
IPC分类号： H03L7/06 , H03L7/087 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit with which phase difference or jitter can be reduced and a clock signal having high phase accuracy can be provided. SOLUTION: When phase difference is generated between both a reference signal 150 and a feedback signal 160, a phase comparator circuit 101 sends the compared result (showing which signal is advanced) to a control pulse generating circuit 154. Then, the circuit 154 changes the charge contents of a charge pump 105 and each time the same compared result is provided, a counter circuit 102 increases the count value. When the compared result is changed, the charge contents are changed just for the value in proportion to the count value corresponding to the changed state. When frequency difference is generated between both signals, this frequency comparator circuit 103 sends the compared result to the control pulse generating circuit 154 and the charge contents are changed in spite of the phase compared result and the count value. Thus, a voltage controlled oscillator 107 is controlled by the output of a waveform dull circuit 106 for which the output of the charge pump 105 and the compared result of the phase comparator circuit 101 are made dull.

10. 发明专利

JPH06295976A MULTI-CHIP MODULE STRUCTURE 失效
公开(公告)号：JPH06295976A
公开(公告)日：1994-10-21
申请号：JP8343293
申请日：1993-04-09
申请人： HITACHI LTD
发明人： TAKENAKA TAKATSUGU , HIDAKA HIROYUKI , YAMAMOTO MASAKAZU , WATANABE YUTAKA
IPC分类号： H01L23/538 , H01L23/522
摘要： PURPOSE:To provide a multi-chip module structure which remarkably improves electric characteristics and wiring accommodation efficiency of a module wiring board mounting LSI chips, ensures high productivity, and has high exchangeability of LSI chips, wiring changeability and manufacturing defect correction capability. CONSTITUTION:This multi-chip module structure constitutes specified function unit by mounting a plurality of LSI chips and mutually connecting them. A plurality of the LSI chips 1 are mutually connected by using a small-sized wiring boards 2 and a large wiring board 3 which have hierarchical structure. Cooling structure 4 is formed on the rear of a plurality of the LSI chips 1. A surface terminal 9 for wiring change and repair use and connection pads of a board- penetrating through hole 13 are formed on the small-sized wiring board 2. A surface terminal 18 for connection change use, connection pads 27 of a board- penetrating through hole 26, and a leading-out connection pad are formed on the large wiring board 3.

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