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31. 发明专利

JPS6451717A LOGIC INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6451717A
公开(公告)日：1989-02-28
申请号：JP20809787
申请日：1987-08-24
申请人： HITACHI LTD
发明人： KOYUI KAORU , KOBAYASHI TORU , YAMADA TOSHIO
IPC分类号： H03K17/30 , H03K19/003 , H03K19/013 , H03K19/086
摘要： PURPOSE:To reduce the soft errors due to alpha-ray in a logic integrated circuit using a VTL circuit by using a transistor(TR) constituting a feedback constant current source, where an embedded layer with a large area is used as the emitter region. CONSTITUTION:Since the area of the collector region of a feedback measuring constant current transistor(TR) Q5 is very small in comparison with the emitter region, the probability of alpha-ray transmission and the quantity of the generated electric charge are decreased, the current flowing to the collector of the TR Qs is less and the fluctuation of a node n2 is suppressed, and the generation of the soft errors due to alpha-ray is reduced. Moreover, the probability of alpha-ray transmitting through the emitter region is increased and the emitter potential is lowered, but a capacitor C is connected in parallel with the emitter resistor R5 of the TR Qs to absorb momentary change in the emitter potential thereby compensating defect due to the increase in the emitter area.

32. 发明专利

JPH0922984A FORMATION METHOD OF INTERCONNECTION 失效
公开(公告)号：JPH0922984A
公开(公告)日：1997-01-21
申请号：JP16951895
申请日：1995-07-05
申请人： HITACHI LTD
发明人： MIZUKOSHI KATSURO , HONGO MIKIO , YAMADA TOSHIO
IPC分类号： H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To obtain a formation method in which it is sufficient to form one each of connecting holes in respective LSI interconnections by a method wherein another mending interconnection is branched and formed from the halfway part of one mending interconnection and the tip of one mending interconnection is changed into a plurality of tips. SOLUTION: When a signal or a power supply from one LSI interconnection 101a is to be supplied to three LSI interconnections 101b, 101c, 101d, a protective film and an insulating film on the LSI interconnections to be connected are removed by using an FIB beam, and a part of the LSI interconnections is exposed. Then, an LSI 100 is placed in a CVD gas atmosphere, the inside of connecting holes 2 is irradiated with an FIB beam or a laser beam 9, a CVD gas is decomposed, and a metal 8 is filled into the connecting holes 2. Then, the laser beam 9 is scanned, and a first mending interconnection 1a is formed across connecting holes at the LSI interconnections 101a, 101c. Then, a laser beam is scanned between the connecting holes 2 at the LSI interconnections 101b, 101d and the prescribed position of the mending interconnection 1a, and a second mending interconnection 1b and a third mending interconnection 1c are formed.

33. 发明专利

JPH08298243A FILM FORMING METHOD AND DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08298243A
公开(公告)日：1996-11-12
申请号：JP10214895
申请日：1995-04-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJIKAWA MASAYUKI , OTSUKA KOJI , YAMADA TOSHIO , MADOKORO YUICHI
IPC分类号： C23C14/22 , C23C16/48 , H01L21/203 , H01L21/205 , H01L21/285
摘要： PURPOSE: To obtain a film uniform in thickness in a film forming technique where an energy beam is used. CONSTITUTION: The regions of a connection hole 1a are irradiated with an FIB 7, wherein the sloping regions (positions B to E and G to J) are set higher in irradiation dose than the flat regions (positions A to B, E to G, and J to K) such as the base or periphery of the connection hole 2a, so that the regions of the connection hole 1a are all set uniform in irradiation density with an FIB 7.

34. 发明专利

JPH05326519A CORRECTION OF SEMICONDUCTOR DEVICE AND DEVICE THEREOF 失效
公开(公告)号：JPH05326519A
公开(公告)日：1993-12-10
申请号：JP12445892
申请日：1992-05-18
申请人： HITACHI LTD
发明人： MIZUKOSHI KATSURO , HONGO MIKIO , SANO HIDEZO , KAMIMURA TAKASHI , TAKADA ATSUKIMI , KAWAJI MOTONORI , YAMADA TOSHIO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To eliminate an adverse effect due to the etching residue of a buffer film formed before the wirings of a semiconductor device are connected by a laser CVD method and to conduct reliably a correction of the device. CONSTITUTION:Lower and upper electrodes 23a and 24 for etching anisotropically an unnecessary part of a buffer film and cylindrical and mesh electrodes 26 and 27 for generating oxidizing or nitrifying radicals are provided in an etching chamber 20 of a wiring connection device. The buffer film of the unnecessary part is removed by anisotropic etching in a degree that damage is hardly exerted on a wiring to be corrected and the like. Then, an etching residue of the buffer film is oxidized or nitrided by the oxidizing or nitrifying radicals to turn the buffer film into a non-conductor.

35. 发明专利

JPH05224850A PRINTER 失效
公开(公告)号：JPH05224850A
公开(公告)日：1993-09-03
申请号：JP2784492
申请日：1992-02-14
申请人： HITACHI LTD
发明人： YAMADA TOSHIO , TSUDA KENICHI , HIRAYAMA RYUICHI , YAMAGUCHI MORIJI
IPC分类号： G06F3/12
摘要： PURPOSE:To enable continuous printing by eliminating the interruption of workability caused by paper exchange in the case of printing when using the form papers in which papers having longitudinal and lateral directions to the feeding direction of the papers are mixed. CONSTITUTION:Character data from an input device 1 are calculated corresponding to the top joining conditions of form paper by a top joining hole detection part 2 and a paper direction detection part 3, and the printing direction is decided by a printing rotation decision part 4 and a printing character direction decision part 6. Therefore, printing is executed by a print control part 8 corresponding to the top joining direction. Thus, an operator can serially input data and print them according to slip format without being troubled by the top joining direction.

36. 发明专利

JPH03178217A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03178217A
公开(公告)日：1991-08-02
申请号：JP31734089
申请日：1989-12-06
申请人： HITACHI LTD
发明人： YAMADA TOSHIO , HAMAMOTO MASATO , SHIMIZU ATSUSHI
IPC分类号： H03K19/086 , H03K19/018 , H03K19/0185
摘要： PURPOSE:To quicken a level change in a transmission signal at the receiving end by providing a discharge circuit selectively energized when an input signal changes from a high level to a low level to the input terminal of a logic gate circuit such as an ECL(Emitter Coupled Logic) circuit or the like. CONSTITUTION:A discharge circuit DC made into an energized state selectively when an input signal changes to a low level, for example, is provided between a ground level and the input terminal of a logic gate circuit such as an ECL circuit or the like. That is, the discharge circuit DC coupled in common with the input terminal of a receiver side logic gate circuit GR is provided to the input terminal of the receiver side logic gate circuit GR. In such a case, a load capacitor coupled with the signal line S at the receiving end of the signal line S is discharged selectively at high speed, e.g. the fall change in the sent signal is speeded up. Thus, the operation of the logic gate circuit is speeded up and the logic integrated circuit device using the ECL circuit as the basic building block is speeded up.

37. 发明专利

JPH02116163A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02116163A
公开(公告)日：1990-04-27
申请号：JP26803688
申请日：1988-10-26
申请人： HITACHI LTD
发明人： TANAKA KAZUO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： H01L21/82 , H01L27/118 , H03K19/173
摘要： PURPOSE:To manufacture the device at a low cost by constructing a voltage follower circuit, which is to transmit reference potential to an ECL circuit, with common circuit components to those of the ECL circuit, and automatically effecting the selection of circuit elements and the design of coupling and wiring, etc., using a DA technique. CONSTITUTION:A bipolar gate array mounts thereon many circuit elements formed in a gate cell area GC of a semiconductor substrate SUB. These circuit elements are connected in a predetermined combination in conformity with a mask formed on the basis of user's specification to construct an ECL circuit such as NOR gate circuits G1-Gn or G, a voltage follower circuit VF1 or VF. Further, the ECL circuit and the voltage follower circuit, etc., are connected in a predetermined combination according to a mask to construct a single digital device. In the bipolar gate array, there is automatically performed through a DA technique using a computer a design concerning the selection of any circuit element or the layout of an ECL circuit and the like, and the coupling and wiring among the circuit elements or the ECL circuits.

38. 发明专利

JPH0233612A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0233612A
公开(公告)日：1990-02-02
申请号：JP18361388
申请日：1988-07-25
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： G06F1/10 , G06F15/78
摘要： PURPOSE:To suppress the crosstalk noises and to ensure the stable and high- speed working of a semiconductor integrated circuit device by crossing periodically a pair of parallel signal lines forming the complementary signal lines to each other. CONSTITUTION:The high-speed clocks received from a clock amplifier CAP are distributed to the clock amplifiers CA1 and CA2 via the complementary signal lines formed with a pair of parallel non-inverted signal lines CD1, inverted signal lines CD1, etc. These complementary signal lines cross each other periodically and therefore the crosstalks of different polarities are periodically eliminated with each other. Thus the crosstalk noises are suppressed. As a result, the stability of high-speed operations can be improved compared with a case where the signal lines are not crossed each other.

39. 发明专利

JPS62105528A HIGH-SPEED LOGIC CIRCUIT WITH EXPANDED OPERATION MARGIN 失效
公开(公告)号：JPS62105528A
公开(公告)日：1987-05-16
申请号：JP24390885
申请日：1985-11-01
申请人： HITACHI LTD
发明人： ITOU HIROYUKI , YAMADA TOSHIO
IPC分类号： H03K19/086
摘要： PURPOSE:To vary the reference voltage to the input signal of a circuit and to increase the operation margin of the circuit by making the current of the feedback circuit of a high-speed logic circuit depend upon variation of a power source for an emitter follower. CONSTITUTION:The input signal VIN of the high-speed logic circuit is compared with the reference voltage VBB by a differential comparing circuit composed of input transistor TRs Q1A-Q1C and a TR Q2 for reference voltage input to sends out an output signal VNOR or VOR. This reference voltage VBB' is obtained from the connection point between collector load resistances RCO1 and RCO2 by the emitter follower TR Q3 and a level shifting resistance RFB and put in phase with the input signal VIN. The quantity of level shifting is determined by the current of a constant current source 2. Then, the current of the feedback circuit is made to depend upon variation of the power source VTT for the emitter follower and the reference voltage to the input signal VIN is varied to increase the operation margin.

40. 发明专利

JPS628393A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS628393A
公开(公告)日：1987-01-16
申请号：JP14474885
申请日：1985-07-03
申请人： HITACHI LTD
发明人： ITOU HIROYUKI , KAWADA ATSUMI , YAGYU MASAYOSHI , YAMADA TOSHIO
IPC分类号： G11C11/41 , G11C11/34 , G11C11/40 , G11C11/414
摘要： PURPOSE:To obtain an LSI having a high integrating degree and a very high freedom degree by using an element which constitutes one ordinary logic gate circuit and forming the memory cell for two bits. CONSTITUTION:Transistors 1 and 2 are a transistor pair for holding the information, an emitter is mutually connected, and a base and a collector are respectively connected to the opponent collector and base. To the common emitter of transistors 1 and 2, a constant electric power source constituted with a transistor 3 and a resistance 8 is connected, and the constant electric current flows to either of the transistor 1 or 2. Respective load resistances 6 and 7 of the transistors 1 and 2 are connected to a word wire W. Transistors 4 and 5 are for the reading and the writing of the information of the memory cell, and respective bases are connected to respective collectors of the transistors 1 and 2. The emitters of the transistors 4 and 5 are connected to reading digit wires DO and DO. The collectors of the transistors 4 and 5 are connected to writing digit wires DI1 and DI2.

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