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1. 发明专利

JP2011059967A Method, device and program for generating stream data 有权
标题翻译：方法，用于生成流数据的设备和程序
公开(公告)号：JP2011059967A
公开(公告)日：2011-03-24
申请号：JP2009208820
申请日：2009-09-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA KAZUO , YOKOYAMA TAKAHIRO , HANAI TOMOHIRO , WATANABE SATOSHI , HANDA ATSURO
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30017
摘要： PROBLEM TO BE SOLVED: To reduce input of stream data into a stream data processing system.
SOLUTION: In a stream data generation method of a computer system for generating stream data having time information attached thereto in time series, and performing stream data processing based on a registered query relative to the generated stream data, the computer system includes a storage part for storing query information showing a constitution element corresponding to the query from the query and a stream definition showing a plurality of kinds of constitution elements constituting the stream data, a data generation part for generating and transmitting the stream data, and a stream data processing part for processing the stream data transmitted from the data generation part. The data generation part generates less stream data from stream data transmitted to the stream data processing part based on the query information.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：将流数据的输入减少到流数据处理系统。解决方案：在用于生成具有时间序列附加到其上的时间信息的流数据的计算机系统的流数据生成方法中，并且基于相对于生成的流数据的注册查询执行流数据处理，计算机系统包括：存储部分，用于存储示出与来自查询的查询对应的构成要素的查询信息，以及流定义，其示出构成流数据的多种构成要素;数据生成部，用于生成和发送流数据;流数据处理部分，用于处理从数据生成部分发送的流数据。数据生成部基于查询信息，从流数据处理部发送的流数据生成较少的流数据。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JPH05312920A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH05312920A
公开(公告)日：1993-11-26
申请号：JP12030892
申请日：1992-05-13
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MARUYAMA YOHEI , HAMAMOTO MASATO , TANAKA KAZUO
IPC分类号： G01R31/28 , H03K19/00
摘要： PURPOSE:To make it possible to perform accurate mounting diagnosis with fewer diagnostic contact patterns. CONSTITUTION:A plurality of flip-flops 20, which are arranged in correspondence with external input pins D1 and D2, are connected in sereis one another. A shift register can output the data, which are inputted through the external input pins for a mounting test to the outside in a serial pattern by sequentially shifting the data. An input circuit 11 is constituted by containing there parts. Thus, diagnostic contact patterns for collecting the data for the mounting test outputted from a semiconductor integrated circuit, which is arranged at the front stage of the semiconductor integrated circuit on a board, can be omitted.

3. 发明专利

JPH05312919A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH05312919A
公开(公告)日：1993-11-26
申请号：JP12030792
申请日：1992-05-13
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MARUYAMA YOHEI , HAMAMOTO MASATO , TANAKA KAZUO
IPC分类号： G01R31/28 , H03K19/00
摘要： PURPOSE:To make it possible to perform accurate mounting diagnosis with fewer diagnostic contact patterns. CONSTITUTION:A plurality of flip-flops 30, which are arranged in correspondence with external output pins Dn-1, Dn, are connected in series one another. A shift register is constituted so that serial data for a mounting test can be sequentially shifted. Each selector 31 can selectively transfer the output of an inner logic circuit 10 and the output of each flip flop 30 to the above described external output pin. The output circuit is constituted by containing these parts. Thus, the parallel outputs of the signals for the mounting test can be outputted from the external output pins. A diagnostic contact pattern between this circuit and an LSI, which is arranged at the rear stage of the LSI, can be omitted.

4. 发明专利

JPH04196462A METHOD FOR WIRING MULTI-LAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04196462A
公开(公告)日：1992-07-16
申请号：JP32759990
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： SAWADA HIROAKI , TANAKA KAZUO
IPC分类号： H01L21/3205 , G11C11/401 , H01L21/82 , H01L23/52
摘要： PURPOSE:To reduce the skew of a clock signal for clock wiring without increasing propagation delay time and complicating a circuit structure by arranging power source wirings on the both sides of the clock wiring. CONSTITUTION:Power source wirings 14 are running in parallel on the both sides of a pair of clock wirings 13 which are clock differential wirings on an optional wiring layer M. Namely, since the power source wiring 14 generally allows less potential change and is more stable compared with the clock wiring 13 and a general signal line 12, the parasitic capacity nonuniformity of the clock wiring 13 which is parallel to the power source wiring 14 is improved. The clock wiring 13 is shielded by the power source wiring 14, waveform deformation caused by a stroke noise between the clock wiring 13 and other general signal line 12 in the same wiring layer M and between the clock wiring 13 and other clock wiring 13 of the same type is surely prevented. Thus, the nonuniformity of the parasitic capacity and the clock signal skew caused by the waveform deformation, etc., are suppressed.

5. 发明专利

JPH01164060A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01164060A
公开(公告)日：1989-06-28
申请号：JP32122787
申请日：1987-12-21
申请人： HITACHI LTD
发明人： YAMADA TOSHIO , KOBAYASHI TORU , TANAKA KAZUO , HAMAMOTO MASATO , IGASHIRA HIROYUKI , SHIMIZU ATSUSHI
IPC分类号： G01R31/28 , G01R31/30 , G06F1/04 , G11C29/00 , G11C29/02 , G11C29/56 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/00
摘要： PURPOSE:To test a saturation margin and an input margin of a gate circuit by a method wherein a bias potential and a reference potential connected to the gate circuit, a memory circuit or the like inside an LSI are changed by an input signal from the outside. CONSTITUTION:This device is constituted by the following: a logic gate part 102 inside a chip 101; a bias-potential generation circuit 103 which feeds a bias potential to the logic gate part; a bias-potential control circuit 104 which changes the bias potential in a step manner. The bias-potential control circuit 104 is connected to the bias-potential generation circuit 103 through a connection 105. In addition, the bias-potential generation circuit 103 feeds the bias potential, a reference potential or the like to the logic gate part 102 through a connection 106. The bias-potential generation circuit 103 changes the bias potential or the like by using a control signal from the bias-potential control circuit 104; it functions in such a way that it maintains an operation margin of a gate circuit 107 within a specified range with respect to a power-supply voltage and a temperature during a normal operation.

6. 发明专利

JPS63122315A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63122315A
公开(公告)日：1988-05-26
申请号：JP26754086
申请日：1986-11-12
申请人： HITACHI LTD
发明人： TANAKA KAZUO
IPC分类号： H03K19/003 , H03K17/60 , H03K19/00 , H03K19/018
摘要： PURPOSE:To prevent the decrease in an output voltage by disconnecting a power voltage line of a Darlington output stage and a power voltage line of its pre-stage to other circuit, providing them in a chip so as to device that the power voltage of the circuit of the pre-stage is not decreased even if the power voltage is decreased due to a large current flowing to the Darlington type output stage. CONSTITUTION:The power voltage of the Darlington output stage and the power voltage of the circuit including an inverter INV are divided into two, output stages of plural cable drivers are connected to a common power voltage line VCC2 and a voltage is supplied to the circuit of the pre-stage including the inverter INV from a power voltage line VCC1. Thus, output signals of the plural drivers are changed to a high level at the same time and a large current such as 70mA flows to each output stage. Then even if the power voltage VCC2 is lowered, the power voltage VCC1 of the circuit of the pre-stage is not subjected to voltage drop. Thus, the base voltage of a transistor Q2 is made stable and a high level VOH of an output voltage VOUT decided based thereupon is not decreased.

7. 发明专利

JPS62139180A SYNCHRONIZING SIGNAL DETECTION SYSTEM 失效
公开(公告)号：JPS62139180A
公开(公告)日：1987-06-22
申请号：JP28142185
申请日：1985-12-11
申请人： HITACHI LTD
发明人： TANAKA KAZUO , OKA TAKASHI
IPC分类号： G11B20/10
摘要： PURPOSE:To obtain a synchronizing signal reproduction circuit with high reliability by supplying a timing pulse generated at a timing generation means to a synchronizing signal detection means, and detecting one synchronizing signal out of plural synchronizing signals. CONSTITUTION:A timing generation circuit 6 monitors a timing, and outputs a gate signal 15 for an SYNC detection, and supplies it to an SYNC detection circuit 8. One additional timing pulse is generated by adding a counter 62, an AND circuit 64, and an OR circuit 65, and when it is impossible to detect an original SYNC, a backup SYNC can be detected. By adding both timing pulses 15 to the SYNC detection circuit 8, either one of an SYNC 2 or an SYNC 2' can be detected at the SYNC detection circuit 8. The output of a demodulation circuit 9 is inputted to an error control circuit, and after an error is corrected, it is outputted to an output device, such as a display device or a printer. Thereby, the synchronizing signal reproduction circuit with high reliability can be obtained.

8. 发明专利

JPS6271329A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6271329A
公开(公告)日：1987-04-02
申请号：JP20996385
申请日：1985-09-25
申请人： HITACHI LTD
发明人： TANAKA KAZUO , USAMI MITSUO , ENOMOTO MINORU
IPC分类号： H03K19/018
摘要： PURPOSE:To prevent the output of a post-stage output circuit from being inverted by providing a clamp means fixing a potential when it is low in level to an output node of an emitter follower circuit. CONSTITUTION:When an input signal Vin higher than a reference voltage VBB in level is inputted and a potential of an output node n1 of a current switch circuit CS goes to a low level, an output node n3 of an emitter follower circuit EF is brought into a potential such as nearly 0.2V lower than a base potential 0.8V of a transistor (TR) Q10 by a forward voltage VF (nearly 0.6V) of a Schottky diode of a Schottky clamp TR Q10. Thus, the potential of the node n1 at the current switch circuit CS is brought into a potential such as nearly 1.0V higher than the potential of the node n3 by the base-emitter voltage VBE of the emitter follower TR Q4. As a result, when the potential of the output node n1 is at a low level, even if the power voltage Vcc rises due to the fluctuation of power supply, the potential at node n1 is clamped to nearly 1.0V.

9. 发明专利

JPS6271241A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6271241A
公开(公告)日：1987-04-01
申请号：JP20996185
申请日：1985-09-25
申请人： HITACHI LTD
发明人： TANAKA KAZUO
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768
摘要： PURPOSE:To construct many types of circuits having different functions by providing a function altering dummy wiring pattern and/or circuit element at least to one of an LSI chip and a mother chip, and selectively providing salient electrodes on the terminals thereof. CONSTITUTION:Assume, for example, that a TTL level is converted to an ECL level. Assume that the input/output level of an LSI chip placed on a mother chip 5 is TTL level. When the LSI chip is connected with a salient electrode 2, the input/output level as a multichip module becomes the TTL level. When the LSI chip is connected with a salient electrode 3, the input/output level as a multichip module becomes the ECL level. Accordingly, if a level converter 6 is associated in the chip 5, the input/output level of the multichip module can be freely switched by the position for placing the LSI chip. Thus, many types of circuits having different functions can be composed.

10. 发明专利

JPS52132702A MODEM INTERFACE SWITCHING SYSTEM 失效
公开(公告)号：JPS52132702A
公开(公告)日：1977-11-07
申请号：JP4966576
申请日：1976-04-30
申请人： HITACHI LTD
发明人： HASHIMOTO TOYOKAZU , TANAKA KAZUO , TAMAKI MASAHIKO
IPC分类号： H04B1/74 , G06F13/00 , H04L1/22 , H04L29/14
摘要： PURPOSE:To enable the fixed length for the interface cable and to relieve the limitation of system layout, by changing the mounting method of the interface switching units.

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