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31. 发明专利

JPH11204939A MULTILAYER CIRCUIT BOARD AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11204939A
公开(公告)日：1999-07-30
申请号：JP219598
申请日：1998-01-08
申请人： HITACHI LTD , HITACHI CABLE
发明人： ISHINO MASAKAZU , TENMYO HIROYUKI , EGUCHI KUNIYUKI , ONDA MAMORU
IPC分类号： B32B27/34 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To eliminate warping of a board and devise reliable inter-layer via- connections by heating an insulation layer for coupling circuit boards having connecting electrodes electrically connected to vias at specified temp. to lower the viscosity below specified leaving it in this temp. range to harden a thermosetting resin layer. SOLUTION: A Cu foil 102 is overlaid on a polyimide film 101 as an insulation sheet, a CO2 gas laser beam reduced in diameter to irradiated it through the polyimide film to form blind vias 103 with the surface Cu foil acting as a stopper, the vias 103 is filled with Cu to form Cu vias 104 with the surface Cu foil 102 used as an electroplating electrode, and electroplating 105 is made. On the back face a protective film 106 is pasted to leave a resist 107 at desired parts, the resist is stripped, the exposed Cu pattern 108 surface is electroless- plated 109, and adhesive 110 is applied on a film circuit surface and thermally compressed.

32. 发明专利

JPH10144723A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10144723A
公开(公告)日：1998-05-29
申请号：JP31553496
申请日：1996-11-12
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI CABLE
发明人： SHIMOISHI TOMOAKI , AKIYAMA YUKIJI , ONDA MAMORU
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To prevent stress from remaining in a inner lead subsequent to a bonding. SOLUTION: In a connection process, a chip 10 is bonded to a tape carrier 1 with an inner lead 4 and outer leads 5, which are laid on one main surface of the chip 10, via an insulating film 8. A notch 6 is formed in the inner lead 4 at a biased position on the inner lead 4. In an inner lead bonding process, the short part 4a of the inner lead 4 is tapped with a bonding tool 13, is cut and thereafter, a cut part piece on the side of the long part 4 of the inner lead 4 is curved by the tool 13 and is thermally pressure-bonded to an electrode pad 12. In a resin sealing process, a silicone rubber is potted in a window hold 3 formed in a carrier main body 2 and a resin-sealed part 14 is formed. Bumps 15 are respectively formed on bump formation holes 7 formed in the outer leads 5. Accordingly, as a stress can be prevented from remaining in the inner lead subsequent to the bonding, the inner lead can be prevented from being disconnected by a thermal stress to act on a CSB(chip size package) and an IC.

33. 发明专利

JPH1041358A TAPE CARRIER FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1041358A
公开(公告)日：1998-02-13
申请号：JP19670296
申请日：1996-07-25
申请人： HITACHI CABLE , HITACHI LTD
发明人： TAGA KATSUTOSHI , OKABE NORIO , KAMEYAMA YASUHARU , ONDA MAMORU , ANJO ICHIRO
IPC分类号： H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To lessen the chip damage due to direct bonding and improve the bond strength at bonding of solder balls to lands. SOLUTION: An insulation film 2 has a device hole 3 at the center in which specified lengths of inner leads 5 and solder ball forming lands 4 flush with the inner leads are exposed. These exposed parts are connected to electrodes of a mounted semiconductor element. An Au plating 8 of 1.0 microns or more is formed on the outer surface of the inner leads 5 and Sn plating 7 is formed on the lands 4.

34. 发明专利

JPH09199535A ELECTRODE STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS PACKAGE FORMATION 失效
公开(公告)号：JPH09199535A
公开(公告)日：1997-07-31
申请号：JP443696
申请日：1996-01-16
申请人： HITACHI LTD , HITACHI CABLE
发明人： ISHINO MASAKAZU , SATO RYOHEI , ONDA MAMORU
IPC分类号： H01L21/60 , H01L23/12 , H01L23/31 , H01L23/498 , H01L21/321
摘要： PROBLEM TO BE SOLVED: To allow conversion of connecting electrodes provided on the peripheral part of an IC (semiconductor integrated circuit) chip into connecting electrodes arranged on all over the chip in a lattice form at low cost and at a shortest wiring distance. SOLUTION: A number of peripheral electrodes 7 per one side of peripheral electrodes 7 arranged on the peripheral part of an IC chip 1 can be indicated by a function of 2i (2i-1), if (i) is granted to be an integer, besides these electrodes 7 are formed being arranged at equal intervals on all sides of a square chip of the IC chip 1 in every equal number besides the chip, whose external connecting electrodes are formed of aluminum, is capsulized with nickel and gold by electroless plating. Later, the peripheral electrodes 7 and an arrangement conversion substrate 2 rearranging the peripheral electrodes 7 into lattice-formed electrodes are electrically connected by metal junction by means of thermal crimping and an interval between the arrangement conversion substrate 2 and the IC chip 1 is filled with adhesive resin 3.

35. 发明专利

JPH0555404A PRINTED WIRING BOARD FOR MOUNTING SEMICONDUCTOR DEVICES 失效
公开(公告)号：JPH0555404A
公开(公告)日：1993-03-05
申请号：JP21258391
申请日：1991-08-26
申请人： HITACHI CABLE , HITACHI LTD
发明人： ONDA MAMORU , FUKUMAKI TAKASHI
IPC分类号： H01L23/14 , H05K1/09 , H05K3/24 , H05K3/34
摘要： PURPOSE:To provide a printed wiring board for mounting semiconductor devices which prevents peeling of a package particularly having a copper based lead frame. CONSTITUTION:A printed wiring board for mounting semiconductor devices comprising a Sn-Pb alloy layer on a printed wiring board 5 with a conductor foil 7 attached to and a Zn layer 8 on the upper surface and/or lower surface of the Sn-Pb alloy layer, and a printed board for mounting semiconductor elements comprising an Zn-Sn-Pb alloy layer on a printed wiring board 5 to which a conductor foil 7 attached.

36. 发明专利

JPH0555298A TAPE CARRIER FOR TAB 失效
公开(公告)号：JPH0555298A
公开(公告)日：1993-03-05
申请号：JP21258191
申请日：1991-08-26
申请人： HITACHI CABLE , HITACHI LTD
发明人： ONDA MAMORU , FUKUMAKI TAKASHI
IPC分类号： H01L21/56 , H01L21/60
摘要： PURPOSE:To obtain a tape carrier for TAB where formation of an intermetallic compound of Cu and Sn is suppressed to prevent the break of an inner lead, by providing Sn alloy plating on Zn or Zn alloy plating on the surface of a copper foil pattern lead. CONSTITUTION:On a copper pattern lead 11 excluding, at least, the inner lead, a Zn or Zn alloy plated layer is made on and further an Sn or Sn alloy plated layer 30 is formed on the surface. In this way, by applying Zn or Zn alloy plating as the base plating of Sn or Sn alloy plating, the formation of the hard intermetallic compound produced by the reaction between Cu and Sn, can be prevented, and the break of the inner lead can be prevented.

37. 发明专利

JPS6237954A LEAD FRAME FOR GLASS SEALED TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6237954A
公开(公告)日：1987-02-18
申请号：JP17739885
申请日：1985-08-12
申请人： HITACHI CABLE , HITACHI LTD
发明人： SANKI SADAHIKO , SATO JUNICHI , ONDA MAMORU , IIZUKA TOMIO , EMOTO YOSHIAKI , TSUCHIDA MINORU
IPC分类号： H01L23/02 , H01L23/48 , H01L23/50
摘要： PURPOSE:To prevent cracking of sealing glass, by providing roundness having a required radius of curvature at the peripheral part of a lead part after blanking, thereby removing stress concentration to the peripheral part of the lead part. CONSTITUTION:The cross sectional shape of a lead part 8 of a part sealed with sealing glass 3 is made to be an approximately rectangular shape by chemical polishing and the like as a whole. The lead part is formed by a flat part, which has a width of 50mum or more and is used for wire bonding, and a peripheral part, which has roundness with the radius of curvature of 0.2mum or more. Then, thermal stress is not concentrated to the sealing glass, which is closely contacted with the lead part 8. Thus, cracking of the sealing glass can be prevented.

38. 发明专利

JPS60147148A LEAD FRAME FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60147148A
公开(公告)日：1985-08-03
申请号：JP313884
申请日：1984-01-10
申请人： HITACHI CABLE , HITACHI LTD
发明人： MATSUYAMA YOSHIHIRO , WATANABE MASARU , ONDA MAMORU , YAMAGISHI RIYOUZOU , YOSHIOKA OSAMU , WAKASHIMA YOSHIAKI
IPC分类号： H01L23/50 , H01L23/28 , H01L23/495
摘要： PURPOSE:To provide a lead frame with excellent adhesion to a mold resin and with highly solderable outer lead sections by a method wherein regions to meet the mold resin and the outer lead sections on a substrate, with its entire surfaced plated with Cu, are provided with plated Sn or an Sn alloy layers and a wire bonding section and die bonding section are covered with an Ag or Au layer. CONSTITUTION:The entire surface of a substrate 10 composed of Fe or an Fe alloy is plated with Cu, and several sections in the Cu coating 8 including regions to meet a mold resin and the outer lead sections are plated with a layer 9 of Sn or Sn-Ni or the like. Further, a die bonding and wire bonding sections in the Cu coating 8 are provided with an Ag layer 6 by plating. Au may be used instead of Ag. When the product is to be used as a semiconductor device, a semiconductor element 5 is fixed to the die bonding section, connected by Au lines or the like to the wire bonding section, and is finally sealed off by a mold resin 7 for the constitution of a semiconductor device. The mold resin runs easily on the surface coated with Sn or an Sn alloy and the surface has an excellent affinity with the mold resin to be hardened later.

39. 发明专利

JPS5156740A DOHIFUKUARUMINIUMU BUSUBAANO DENSETSUMENSHORIHOHO 失效
公开(公告)号：JPS5156740A
公开(公告)日：1976-05-18
申请号：JP13108574
申请日：1974-11-15
申请人： HITACHI CABLE , HITACHI LTD
发明人： HANAMI TAKEMITSU , DEIITORITSUHI EERUSHUREEGERU , SANKI SADAHIKO , ONDA MAMORU , SAITO YOSHIO , SAITO TADASHI
IPC分类号： H01R11/11 , C25C7/00 , C25C7/02 , C25D7/00 , C25D17/00 , C25D17/12 , H01R25/16

40. 发明专利

JP2000294933A MULTILAYER CIRCUIT SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000294933A
公开(公告)日：2000-10-20
申请号：JP9714199
申请日：1999-04-05
申请人： HITACHI LTD , HITACHI CABLE
发明人： ISHINO MASAKAZU , TENMYO HIROYUKI , ONDA MAMORU , SATO TAKASHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To improve the heat resistance property of a junction metal by using tin plating with copper ground as the junction metal of a via for electrically connecting a plurality of adjacent circuit boards and forming a tin/copper alloy for electrical connection. SOLUTION: A copper foil 102 is affixed to a polyimide film 101 as an insulation layer, a laser beam is applied from the reverse side of the film 101, and a blind via 103 where the surface copper foil 102 becomes a stopper is formed. A copper via 104 is formed so that a salient electrode can be formed by filling plating copper into the via 103. After that, a protective film 106 is affixed to the reverse side of the film 101, and a photolithographic process is made, thus allowing a resist 107 to remain at a required part. With the resist 107 as a mask, unwanted copper is eliminated by etching and a copper foil pattern 108 is formed, then a tin layer is laminated, and further an adhesive film 110 is affixed to the reverse side of the film 101 and is subjected to thermocompression bonding, thus forming a tin/copper alloy for electrical connection.

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