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31. 发明专利

JPS57192073A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57192073A
公开(公告)日：1982-11-26
申请号：JP7656081
申请日：1981-05-22
申请人： HITACHI LTD
发明人： SHIMIZU SHINJI , MIYAZAWA HIROYUKI , KASAHARA OSAMU
IPC分类号： H01L21/768 , H01L21/28 , H01L29/43 , H01L29/45
摘要： PURPOSE:To perform easily the heat treatment of impurity diffusion, etc., at a semiconductor device wherein a wiring layer is coming in contact with a semiconductor substrate directly by a method wherein the wiring layer is formed in laminated structure of an amorphous semiconductor - a high melting point metal. CONSTITUTION:Field SiO2 films 2 are made to grow on the main face of a P type silicon substrate 1, and after an oxidation resistive mask is etched, thin gate oxide films 15 are made to grow, and an opening 16 is formed by etching. Then the amorphous silicon film 13 and the molybednum film 14 are adhered in succession using the same sputtering device. Then phosphorus is made to diffuse in the silicon crystal of the substrate 1 at the region of the opening 16 through the molybdenum film 14 and the amorphous silicon film 13 to form the N type region 4a. Moreover a gate electrode and wiring 7, 8 and openings are formed respectively by etching, and the N type regions 4, 5, 11 are formed as the source or drain regions by the ion implantation method.

32. 发明专利

JPS5364468A SILVER WIRE CONNECTING METHOD 失效
公开(公告)号：JPS5364468A
公开(公告)日：1978-06-08
申请号：JP13958276
申请日：1976-11-22
申请人： HITACHI LTD
发明人： KIKUTA AKIRA , OOKUBO TADASHI , ISHIDA HIROYUKI , KASAHARA OSAMU
IPC分类号： H01L21/60
摘要： PURPOSE:To increase the reliability of bonding of silver wires and solder or lead wires by performing welding in an inert atmosphere or reductive atmosphere not containing oxygen.

33. 发明专利

JPS52156475A DEVICE FOR INVERTING*FEEDING PARTS 失效
公开(公告)号：JPS52156475A
公开(公告)日：1977-12-26
申请号：JP7314376
申请日：1976-06-23
申请人： HITACHI LTD
发明人： YOSHIDA MAKOTO , OOMAE MINE , KASAHARA OSAMU
IPC分类号： B23P19/00 , H01L21/50 , H01L21/68 , H01L23/00 , H01L23/04
摘要： PURPOSE:To feed a stem onto a welding table with automatically inverting it in a sealing of a can-seal type semiconductor device and to improve the working efficiency.

34. 发明专利

JPS51142976A SEMICONDUCTOR DEVICES AND THEIR PRODUCTION METHOD 失效
公开(公告)号：JPS51142976A
公开(公告)日：1976-12-08
申请号：JP6655075
申请日：1975-06-04
申请人： HITACHI LTD
发明人： TOMOSAWA AKIHIRO , NAKADA KENSUKE , KASAHARA OSAMU
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To lower the rate of silicon content of the semiconductor device, having electrodes of aluminum including silicon, to such an extent that the preventive effect of junction break-down is maintained.

35. 发明专利

JPH0917732A MANUFACTURE OF SEMICONDUCTOR AND EQUIPMENT 失效
公开(公告)号：JPH0917732A
公开(公告)日：1997-01-17
申请号：JP16025195
申请日：1995-06-27
申请人： HITACHI LTD , KOKUSAI ELECTRIC CO LTD
发明人： OKAWA AKIRA , TERASAKI TADASHI , KASAHARA OSAMU , ANDO TOSHIO
IPC分类号： C23C16/44 , C23C16/455 , H01L21/02 , H01L21/205
摘要： PURPOSE: To enhance the yield of semiconductor wafer and the operation rate for semiconductor manufacturing equipment by discharging air to a vacuum state from a container, passing a process gas to a porous member provided at a gas introducing portion, introducing the gas inside a cylindrical member, and treating an article within the cylindrical member. CONSTITUTION: Air is discharged to a vacuum state from a vacuum treatment chamber 2b by a vacuum air discharge pump 7 to a predetermined pressure. Thereafter, a process gas is introduced to a gas introducing portion 5a communicating with an outer pipe member 3 of a vacuum treatment container 2. Here, a process gas or inert gas is passed to a plurality of porous members 6 provided at a gas introducing portion 5a. Thereafter, a predetermined amount of heated and filtered gas is introduced inside a cylindrical member 3 and an inner piper member 4. Here, a vacuum treatment container 2 is heated by second heating means 13 such as a resistance heater, and the vacuum treatment chamber 2b is set to a predetermined temperature and a semiconductor wafer 1 is heated.

36. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

37. 发明专利

JPH06140572A FORMATION OF CAPACITIVE INSULATING FILM 失效
公开(公告)号：JPH06140572A
公开(公告)日：1994-05-20
申请号：JP29098392
申请日：1992-10-29
申请人： HITACHI LTD
发明人： KASAHARA OSAMU , SAKUMA HIROSHI , TSUCHIYA OSAMU , SUGIURA JUN
IPC分类号： H01L21/205 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To provide a silicon nitride film having a film thickness with sufficient charge storage capacity, by changing a gas to an SiH3Cl2 gas halfway after an NH3 gas is supplied at first under lowering pressure in an initial kernel forming process, and also changing the gas halfway to the SiH3Cl2 gas after the NH3 gas is supplied under given pressure in a film growth process. CONSTITUTION:A growing process of a natural oxide film 11 over a lower electrode 2 is controlled by using a CVD system with a load lock mechanism so that a natural oxide film 11 can be made thin. In addition, an initial kernel forming process and a film growth process are carried out, in which a silicon nitride film 10 and a silicon nitride oxide film 11 obtained by oxidizing the silicon nitride film 10 are formed with their film thicknesses enough to hold a sufficient charge storage capacity. Then, a capacitive insulating film 1 thicker than a conventional one can be obtained. In this initial kernel forming process, the silicon nitride film 10 is grown on the silicon oxide at a rate nearly equal to that of the growth on the silicon. Consequently, a silicon nitride film 10 with sufficient film thickness, along with good acid-proof characteristics, can be obtained even on the silicon nitride film.

38. 发明专利

JPH0429354A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0429354A
公开(公告)日：1992-01-31
申请号：JP13383390
申请日：1990-05-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIZAWA HIROTAKA , MIYAMA MASANORI , AZUMA SEIICHIRO , KASAHARA OSAMU , SUZUKI SHINICHI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L29/732
摘要： PURPOSE:To micrify and highly integrate an integrated circuit by isolating elements by the use of U-grooves and filling the grooves with an insulator. CONSTITUTION:The principal face of a semiconductor substrate 1 is etched and a shallow first groove OP1 is made to surround the active region in which active elements are formed. A part of the bottom of the shallow first groove OP1 is etched to make a deep second groove 4a narrower than the first groove OP1. An insulating film 6 is formed on the principal face of the semiconductor substrate 1 including the first and second grooves OP1 and 4a by accumulating an insulator by the CVD method. The insulating film 6 is anisotropically etched back to remove the insulating film 6 on the active region with that in the first and second grooves OP1 and 4a left remaining. Thereby higher integration is achieved and a manufacture process is simplified.

39. 发明专利

JPH02299267A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02299267A
公开(公告)日：1990-12-11
申请号：JP12078089
申请日：1989-05-15
申请人： HITACHI LTD
发明人： OWADA NOBUO , KASAHARA OSAMU , ASANO ISAMU , TAMARU TAKESHI
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/40 , H01L29/732
摘要： PURPOSE:To enable the miniaturization of a bipolar LSI and to enable it to operate at a high speed by a method wherein an opening is provided to a part of an element isolation insulating film adjacent to the base diffusion layer of the bipolar transistor to form a collector lifting layer. CONSTITUTION:An opening is provided to an element isolation insulating film 6 in contact with insulating films 15 and 10 and a base diffusion layer 8 through etching to form a contact hole 16c whose base reaches to a collector buried layer 2, and then a collector lifting layer 19 is formed by filling a tungsten film into the contact hole 18c. A barrier metal layer 20 and an aluminum film 21 are successively deposited thereon, which is etched to form a base electrode 22, an emitter electrode 23, and a collector electrode 24. In this case, the space between the base diffusion layer 8 and the collector lifting layer 19 can be made small and the collector lifting layer 19 small in resistance can be obtained. By this setup, a bipolar transistor of this design can be miniaturized and made to operate at a high speed.

40. 发明专利

JPH02277231A METHOD AND APPARATUS FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02277231A
公开(公告)日：1990-11-13
申请号：JP9854889
申请日：1989-04-18
申请人： HITACHI LTD
发明人： OWADA NOBUO , KASAHARA OSAMU
IPC分类号： H01L21/285 , H01L21/28
摘要： PURPOSE:To prevent reliability of a connection hole from being lowered due to an abnormal growth of a tungsten (W) film by a method wherein film-formation parameters such as a flow rate of a reaction gas, a substrate temperature and the like are changed with the passage of time and the W film is grown intermittently. CONSTITUTION:A substrate 1 is housed in a low-pressure CVD apparatus 20 in order to fill a W film into the inside of a contact hole; the semiconductor substrate 1 is arranged and supported, in a state that a formation face of an integrated circuit is faced downward, on the bottom face of a hot chuck 23 installed in the center at the upper part of a chamber 21. A heating source 26 directly heats the rear of the substrate 1; its output is changed by using an output control means 27 at a desired cycle//; a reaction-gas supply source which has been filled with WF6 gas and silane gas is connected to one end of a reaction-gas introduction port 28 at the bottom part of the chamber 21; a flow rate of the reaction gases and their mixture ratio are changed by using a flow-rate control means 31 at a desired cycle. Thereby, it is possible to effectively prevent crystal particles from becoming coarse and large by an abnormal growth operation of the W film; it is possible to enhance reliability of a connection hole.

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