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31. 发明专利

JP2003085121A Memory device 有权
标题翻译：内存设备
公开(公告)号：JP2003085121A
公开(公告)日：2003-03-20
申请号：JP2001270518
申请日：2001-09-06
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SENBA SEIJI , NISHIO YOJI
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/06 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175 , G11C11/409
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/10 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To provide a memory device capable of reducing waveform distortion by reflection caused at high speed operation time in the memory device for mounting a controller on a mother board together with a plurality of memory modules.
SOLUTION: This memory device is obtained with the constitution for arranging an active terminator in the controller and a memory unit since signal reflection is caused at writing and reading time of the memory unit on the memory modules by the controller. The active terminator is arranged in response to a data bus and/or a clock bus. The active terminator is arranged for terminating a line in the memory unit corresponding to the data bus and the clock bus. The active terminator arranged in the controller and the memory unit may be controlled in a nonoperating state when becoming the data receiving side.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种能够在用于将控制器与多个存储器模块一起安装在母板上的存储装置中在高速操作时间引起的反射减少波形失真的存储装置。解决方案：由存储器单元的写入和读取时间由控制器在存储器模块上引起信号反射，从而获得用于将有源终端器布置在控制器中的结构和存储单元的存储器件。有源终端器响应于数据总线和/或时钟总线被布置。有源终端器被安排用于终止对应于数据总线和时钟总线的存储器单元中的一行。布置在控制器和存储器单元中的有源终端器在成为数据接收侧时可以被控制在非操作状态。

32. 发明专利

JP2009254056A Inverter apparatus 有权
标题翻译：逆变器装置
公开(公告)号：JP2009254056A
公开(公告)日：2009-10-29
申请号：JP2008096698
申请日：2008-04-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SENBA SEIJI
IPC分类号： H02M1/08 , H02M1/00 , H02M7/48 , H03K17/16 , H03K17/56
摘要： PROBLEM TO BE SOLVED: To effectively avoid inverse surge between a reference potential terminal of a signal for driving a high potential side IGBT and a reference potential terminal of a gate drive IC even in an inverter apparatus which feeds a large current to a power module. SOLUTION: An inverter apparatus comprises: an IGBT module 113 having a high potential side IGBT 121 and a low potential side IGBT 123; a gate drive IC 101 for driving the high potential side IGBT 121 and the low potential side IGBT 123; a capacitor 128 provided between a reference potential terminal 106 for high potential side IGBT driving signal of the gate drive IC 101 a collector terminal 117 of the low potential side IGBT 123; and a resistor 127 provided between the reference potential terminal 106 for high potential side IGBT driving signal of the gate drive IC 101 and an emitter terminal 116 of the high potential side IGBT 121. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了有效地避免用于驱动高电位侧IGBT的信号的参考电位端子与栅极驱动IC的基准电位端子之间的反向浪涌，即使在向大电流馈电的逆变器装置中电源模块解决方案：逆变器装置包括：具有高电位侧IGBT 121和低电位侧IGBT 123的IGBT模块113; 用于驱动高电位侧IGBT 121和低电位侧IGBT 123的栅极驱动IC 101; 设置在栅极驱动IC101的高电位侧IGBT驱动信号的基准电位端子106和低电位侧IGBT123的集电极端子117之间的电容器128; 以及设置在栅极驱动IC101的高电位侧IGBT驱动信号的基准电位端子106和高电位侧IGBT 121的发射极端子116之间的电阻器127.（C）2010，JPO＆INPIT

33. 发明专利

JP2003133943A INPUT/OUTPUT CIRCUIT, REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2003133943A
公开(公告)日：2003-05-09
申请号：JP2001331397
申请日：2001-10-29
申请人： ELPIDA MEMORY INC
发明人： SENBA SEIJI
IPC分类号： H03K19/0175 , H03F1/56 , H03F3/62 , H03K19/0185 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide an input/output circuit equipped with a termination circuit which restrains increase in the chip area. SOLUTION: The circuit is provided with an output buffer, an input buffer 10 and a control circuit 20. The output buffer consists of a 1st series circuit comprised of a transistor MP11 and a resistor R11, and a 2nd series circuit comprised of a transistor MP12 and a resistor R13 which are connected in parallel between a high-level side power supply VDDQ and an input/output terminal DQ, a 3rd series circuit comprised of a transistor MN11 and a resistor R12, and a 4th series circuit comprised of a transistor MN12 and a resistor R14 which are connected in parallel between a low-level side power supply GND and the input/output terminal DQ. The input buffer 10 where its input terminal is connected to the input/output terminal DQ. The control circuit 20 which controls at output, common supply of the signal that is obtained by inverting output data to the gates of the transistors MP11, MP12, MN11, and MN12, and at input, applying the VDDQ and the GND power supply voltages respectively to the gates of the transistors MP11 and MN11, and applying the GND and the VDDQ power supply voltages respectively to the control terminals of the transistor MP12 and the MN12.

34. 发明专利

JP2001183422A SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC CIRCUIT 失效
公开(公告)号：JP2001183422A
公开(公告)日：2001-07-06
申请号：JP36879499
申请日：1999-12-27
申请人： HITACHI LTD
发明人： SENBA SEIJI , NISHIO YOJI
IPC分类号： G01R31/28 , G06F12/00 , G06F13/16 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/02 , H01L21/822 , H01L27/04 , H03K19/0175 , H05K1/02 , H05K1/14
摘要： PROBLEM TO BE SOLVED: To suppress ringings, occurring on a transmission line in conformity with the situation of a packaged system even when high-speed operation with small signal amplitude. SOLUTION: Dummy wiring 25 is provided simulating actual wiring 26, that connects semiconductor integrated circuits 2, 6 on a circuit board. The integrated circuits have a data output circuit 28 with a variable slew rate and a circuit 29 for measuring signal delay time from a signal send-out point to a signal reflection point (characteristic impedance mismatch point) by using the dummy wiring 25. Signal transition time of the output circuit is determined, by using the delay time obtained by the measuring circuit. The transition time is at least twice the delay time, which extends from the send-out point to the nearest branch of the wiring. This enables transmission of signals with mitigated reflection by the nearest reflection point.

35. 发明专利

JPH07129652A CIRCUIT DATA DISPLAY METHOD AND CIRCUIT DATA INPUT METHOD USING THE SAME 失效
公开(公告)号：JPH07129652A
公开(公告)日：1995-05-19
申请号：JP27805893
申请日：1993-11-08
申请人： HITACHI LTD
发明人： SENBA SEIJI , YOKOMIZO KOICHI
IPC分类号： G06F17/50
摘要： PURPOSE:To simultaneously display a circuit diagram and circuit characteristics on one screen by displaying the circuit characteristics by the positions of nodes and the shape and size of element symbols in the circuit diagram. CONSTITUTION:The input of the circuit diagram is performed by arranging the element symbols and connecting terminals by wiring elements. Then, the nodes are arranged so as to be lined in a vertical direction on the screen. in this case, the screen is composed of a scale b4 for expressing the correspondence of a node voltage and the vertical direction on the screen, a result display b3 and a means b8 for specifying the analysis time. Before and after the result display, the positions of the nodes in the vertical direction on the screen in the circuit diagram are changed. In the result display, a transient analysis result at the time of 6.2 nanoseconds is indicated and it is indicated that the voltage of the node b5 is 15V, the voltage of the node b6 is 5V and the voltage of the node b7 is 2V. In the case of referring to a circuit simulation result at the other analysis time, by shifting the slider of the b8, the time is changed and the display is performed.

36. 发明专利

JP2001067875A OUTPUT CIRCUIT 失效
公开(公告)号：JP2001067875A
公开(公告)日：2001-03-16
申请号：JP24118099
申请日：1999-08-27
申请人： HITACHI LTD
发明人： SENBA SEIJI , NISHIO YOJI , NAKAGOME YOSHINOBU
IPC分类号： G11C11/409 , G11C11/407 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To stabilize the operation of a synchronous DRAM or the like with an output circuit and a memory module or the like with it by suppressing ringing when shifting to high-impedance state in a tri-state-type output circuit. SOLUTION: A tri-state-type output circuit is provided with a NOR gate NO1 including a MOSFETN 2 that is turned on selectively by setting an output control signal DOC to a low level and its inversion signal DOCB to a high level and turning off a corresponding N-channel-type output MOSFET by setting a output signal DOBN to a low level. In this case, for example, a damping resistor Rd2 for making gentle the change to the low level of the output signal DOBN and for making gentle the transition to the off state of the N-channel- type output MOSET is provided in series with, for example, the MOSFETN 2.

37. 发明专利

JPH1185822A METHOD AND DEVICE FOR SUPPORTING CIRCUIT DESIGN AND STORAGE MEDIUM STORED WITH CIRCUIT DESIGN SUPPORTING PROGRAM 失效
公开(公告)号：JPH1185822A
公开(公告)日：1999-03-30
申请号：JP23927797
申请日：1997-09-04
申请人： HITACHI LTD
发明人： SENBA SEIJI , KITAGAWA AKIHIRO , YOKOMIZO KOICHI
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To reduce the time required for circuit constant optimization processing and to update a library in a short period by making the gate width and gate length of a MOS transistor as variable and making the difference between an element value of an equivalent circuit in a design circuit and a corresponding element value of an equivalent circuit in the existing circuit as an evaluation function. SOLUTION: A design circuit equivalent circuit element value calculating part 4 calculates the element value of an equivalent circuit in a design circuit, based on a result of circuit simulation in a circuit simulating part 3 and data D5. A circuit constant correcting part 5 corrects a circuit constant that is a constant in a design circuit, based on a calculation result of the element value the equivalent circuit in the design circuit, so that the element value of the equivalent circuit in the design circuit can approach a corresponding to element value of an equivalent circuit in the existing circuit. The correction is realized by using a nonlinear minimization method that minimizes it with the error of each element value of the equivalent circuit in the design circuit to a corresponding element value of an equivalent circuit of the existing circuit as an evaluation function.

38. 发明专利

JPH08222697A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH08222697A
公开(公告)日：1996-08-30
申请号：JP2494595
申请日：1995-02-14
申请人： HITACHI LTD
发明人： SENBA SEIJI , KANBARA SHIRO , YOKOMIZO KOICHI
IPC分类号： H01L21/31 , H01L21/762 , H01L21/822 , H01L27/04
摘要： PURPOSE: To suppress noise propagation from a digital circuit to an analog circuit in an analog/digital mixed semiconductor integrated circuit. CONSTITUTION: Analog or digital circuits 3, 4 are formed inside a pot structure clear of a part of an insulator film 2 forming the inside of the pot structure having the side and the bottom consisting of an insulator in a silicon substrate 1. Thereby, noise suppressing effect equal to the case where an SOI substrate is used without using an expensive SOI substrate can be obtained, thus allowing an improvement of analog signal accuracy at a low cost.

39. 发明专利

JPH08161363A METHOD FOR SUPPORTING CIRCUIT DESIGN 失效
公开(公告)号：JPH08161363A
公开(公告)日：1996-06-21
申请号：JP30457594
申请日：1994-12-08
申请人： HITACHI LTD
发明人： SENBA SEIJI , YOKOMIZO KOICHI , KANBARA SHIRO
IPC分类号： G06F17/50
摘要： PURPOSE: To save the handling time of repeating element circuit design where an errorneous specification is allotted by preventing the errorneous specification from being allotted to an element circuit. CONSTITUTION: This system is provide with a processing for reading the specification of the whole circuit and an arithmetic expression to roughly calculate whole circuit performance more than element circuit performance as inputs, a database 12 including the design data of the element circuit having variation both in the input and a function and performance, an element circuit combination retrieval processing 13b retrieving the combination of the element circuits meeting the whole circuit specification from the database 12 and an element circuit output processing 14 executing an output when the relevant element circuit exists. An element circuit extraction processing extracting the element circuit with a performance value equal to below a fixed reference value from the database 12 is also provided.

40. 发明专利

JP2001256772A MEMORY MODULE 失效
公开(公告)号：JP2001256772A
公开(公告)日：2001-09-21
申请号：JP2000072484
申请日：2000-03-10
申请人： HITACHI LTD
发明人： SENBA SEIJI , NAKAGOME YOSHINOBU , HORIGUCHI SHINJI , NISHIO YOJI
IPC分类号： G06F1/18 , G06F3/00 , G06F13/16 , G11C5/00 , H01L23/50 , H01L23/538 , H01L25/04 , H01L25/065 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a memory module capable of improving reliability of signal transmission by diminishing disturbance of a signal wave due to reflection of the signal, and controlling increase in an access time. SOLUTION: A module substrate (10) has plural module data terminal pairs (24L, 24L) individually arranged corresponding to each chip data terminal (Dm) of plural memory chips (1), and plural module data wiring (15) respectively connecting between the plural module terminal pairs. The plural module data wiring (15) are respectively connected with the corresponding chip data terminals, and are formed to be usable as a memory access data bus. In a memory system wherein plural pieces of memory modules are arranged in parallel, the module data wiring of each memory module are connected in series, and individual module data wiring do not form branch wiring to the data bus on a mother board of the memory system. Parallel access of the number of bits in accordance with a bus width of a memory access data bus is secured for the memory modules.

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