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1. 发明专利

JPH1041396A LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH1041396A
公开(公告)日：1998-02-13
申请号：JP19729296
申请日：1996-07-26
申请人： HITACHI LTD
发明人： SENBA SEIJI , YOKOMIZO KOICHI , ICHIKI SHUZO , KITAGAWA AKIHIRO , OTSUKA MASANORI , TSUKADA TOSHIRO
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To minimize the correcting points of a mask layout after the optical shrink, if it must be corrected to expand individual devices by forming spare regions of specified area round the devices. SOLUTION: A spare region 9 of an area 1 to 3 times the area of a corresponding device 7 is provided round the device 7 which gives importance on the matching accuracy in the mask layout at the time of a new design. A spare region 9 of e.g. the same area as that of the device 7 is formed at the left of the device 7 to be a voltage divider resistor which gives importance on the matching accuracy. This results in that the correcting point required for expansion correction of the device which gives importance on the matching accuracy after the optical shrink never has effect on other devices. The increase of the chip area for the spare region is suppressed to min. required for the efficient update of the functional IC library.

2. 发明专利

JPH0897400A VACUUM ELECTRON BEAM INTERFERENCE DEVICE 失效
公开(公告)号：JPH0897400A
公开(公告)日：1996-04-12
申请号：JP23478294
申请日：1994-09-29
申请人： HITACHI LTD
发明人： NISHIYAMA HIDETOSHI , KURODA KATSUHIRO , OSHIMA TAKU , OKAMOTO MASAKUNI , KITAGAWA AKIHIRO
IPC分类号： H01L29/06 , H01J21/10 , H01L29/66
摘要： PURPOSE: To comprises a switch, an amplifier element or a logic circuit normally operating at a room temperature or under radioactive rays by a method where there are in a vacuum arranged a screen plate having holes behind the anode arranged facing an electron beam source, and an electron collecting electrode capable of applying a positive voltage to the electron beam source and located further behind the screen plate. CONSTITUTION: When a positive high voltage is applied to an field-emission electron beam source 1, electrons are taken out in a vacuum towards an anode 2. The anode 2 has holes of about 2μm so that the accelerated electrons advance backwardly. Further, the electrons pass through hole 4 in a screen plate 3 composed of a plate of W and are collected to an electron collecting electrode 7. Incidentally, the holes 4 are a circle having a diameter of about 0.1μm so that a quantum level can be performed by applying a voltage. Therefore, the wave number of electrons passing through the holes 4 is limited to a few and the strength distribution of electrons specially occurs due to interference effects among electrons having a different wave number. Accordingly, by a change of a voltage V4 applied to the holes 4, a current value 1 obtained from the electron collecting electrode 7 is changed and this current value change is used.

3. 发明专利

JPH07294594A NOISE EVALUATION DEVICE OF INTEGRATED CIRCUIT AND NOISE REDUCING METHOD USING IT 失效
公开(公告)号：JPH07294594A
公开(公告)日：1995-11-10
申请号：JP9151094
申请日：1994-04-28
申请人： HITACHI LTD
发明人： FUKUDA KEIKO , KITAGAWA AKIHIRO
IPC分类号： G01R31/26 , G01R29/26 , G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To measure and evaluate the influence of noise generated by a digital circuit to an analog circuit before the mixing by inputting noise to a substrate noise input part and measuring the influence of the noise. CONSTITUTION:A pseudo signal is supplied from a signal generation circuit 4 to a noise input part 2, a circuit 3 to be evaluated measures the influence of noise, and the value is input to a means (data processing device) 5 for measuring the influence of the noise. Also, a signal input from the input part 2 is transferred to a substrate power supply input part 6, where the level of the signal generated by the input part 6 is measured and the level of substrate fluctuation is examined. Then, the device 5 includes an A/D converter, a data collector, and a signal processor when the circuit 3 outputs an analog voltage value then the device 5 consists of the data collector and the signal processor when the circuit 3 outputs a digital voltage value. These signal processing parts measure, process, and display the amplitude, power, frequency characteristics, waveform etc. of a noise signal.

4. 发明专利

JPH0715330A A/D CONVERTER AND A/D CONVERSION METHOD 失效
公开(公告)号：JPH0715330A
公开(公告)日：1995-01-17
申请号：JP15858893
申请日：1993-06-29
申请人： HITACHI LTD
发明人： KITAGAWA AKIHIRO , KIKUCHI TAKAFUMI
IPC分类号： H03M1/14 , H03M1/34
摘要： PURPOSE:To attain a high processing speed with a simple configuration by arranging alternately a connecting point of a voltage comparator for extracting a reference voltage and a switch connecting point among connecting points of resistors of a resistor array. CONSTITUTION:An A/D converter 20 includes a resistor array 201 and a voltage comparator group 202 to generate a digital output corresponding to a differential analog input. Furthermore, a differential D/A converter 30 includes a resistor array 201 and a switch group 301 to generate an analog voltage corresponding to a digital value being the result of A/D conversion by the converter 20 via a switch 301. Then the A/D converter provided with a differential input operational amplifier 50 obtains a difference between an output VDAC of the converter 30 and a differential analog input voltage Vin. A connecting point of a voltage comparator 201 for extracting a reference voltage and a connecting point of the switch 301 among connecting points of the resistors of the resistor array 201 are arranged alternately. Then the operating speed of the differential amplifier 50 is improved and a high processing speed is realized with a simple configuration.

5. 发明专利

JPH11239059A DIGITAL-TO-ANALOG CONVERTER 失效
公开(公告)号：JPH11239059A
公开(公告)日：1999-08-31
申请号：JP3843898
申请日：1998-02-20
申请人： HITACHI LTD
发明人： ICHIKI SHUZO , OTSUKA MASANORI , KITAGAWA AKIHIRO
IPC分类号： H03M1/68 , H03M1/74
摘要： PROBLEM TO BE SOLVED: To obtain a DA converter which makes the voltage of a power supply low, also reduces the number of transistors and has high accuracy. SOLUTION: This converter is provided with a termination circuit of low input impedance which mutually connects each current input terminal of plural differential current switches 110, connects a current source 101 to the connection points and operates a MOS transistors constituting the switches 110 in an on state in a linear area. The operation of the switches 110 is controlled in response to a digital signal and an analog signal is outputted from the termination circuit. The inter-gate/source voltage that turns on the MOS transistors of the switches 110 is set lower than the inter-drain/source voltage of a conventional current source transistor.

6. 发明专利

JPH11233714A METHOD OF REDUCING NOISE OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND ITS CIRCUIT 失效
公开(公告)号：JPH11233714A
公开(公告)日：1999-08-27
申请号：JP2793198
申请日：1998-02-10
申请人： HITACHI LTD
发明人： FUKUDA KEIKO , TSUKADA TOSHIRO , KITAGAWA AKIHIRO
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To offset board coupling noise which occurs centering upon the highest DC potential or lowest DC potential on a semiconductor board. SOLUTION: This noise reduction method detects board coupling noise 14 through a capacitor C2 from a board noise detecting region 1, and inputs a detection signal into the inverted input terminal 4 of an offset signal generating circuit 3. This supplies an offset signal input region 2 with an offset signal to negate board coupling noise through a capacitor C1 from the output terminal 5 of the offset signal generating circuit 3. Hereby, this can feed back only an AC signal independently of the DC potential of the board, so this can drive the offset signal generating circuit with the same single power source as an integrated circuit.

7. 发明专利

JPH07202695A CIRCULATION TYPE AD CONVERTER 失效
公开(公告)号：JPH07202695A
公开(公告)日：1995-08-04
申请号：JP33829293
申请日：1993-12-28
申请人： HITACHI LTD
发明人： KITAGAWA AKIHIRO , KIKUCHI TAKAFUMI , MATSUURA TATSUJI
IPC分类号： H03M1/14
摘要： PURPOSE:To improve conversion speed without increasing circuit scale and power consumption in a circulation type AD converter. CONSTITUTION:In a circulation type AD converter, the time required for the setting of the output of a DA converter 50 and the amplification time of an amplifier 63 are made separate clock timing by providing a switch 90 in the input part of a sub-AD converter 30, and further, inserting a latch circuit 40 between the sub-AD converter 30 and the DA converter 50. The signal path in single clock timing is shortened, the raising of a clock frequency is enabled without speeding up each component of the circulation AD converter and a high speed circulation AD converter is composed by low power consumption.

8. 发明专利

JPH07297720A COMPARATOR 失效
公开(公告)号：JPH07297720A
公开(公告)日：1995-11-10
申请号：JP8616794
申请日：1994-04-25
申请人： HITACHI LTD
发明人： TSUKADA TOSHIRO , FUKUDA KEIKO , KITAGAWA AKIHIRO
IPC分类号： G01R19/165 , H03K5/08 , H03M1/34
摘要： PURPOSE:To provide a comparator comprising the same circuit configuration as that of a digital circuit, that is, comprising digital logic gates to allow the comparator to cope with a low power supply voltage applied to an integrated circuit. CONSTITUTION:A couple of inverters 5 being digital logic gates are arranged and an output in response to a voltage applied to an input terminal of each inverter is differentially amplified by a latch 3 having a couple of input terminals or a flip-flop circuit and the result of comparison is outputted as a result. Thus, an analog/digital hybrid large scale integrated circuit coping with a low voltage power supply is easily designed and manufactured.

9. 发明专利

JPH07282595A SAMPLE-HOLD CIRCUIT 失效
公开(公告)号：JPH07282595A
公开(公告)日：1995-10-27
申请号：JP7046894
申请日：1994-04-08
申请人： HITACHI LTD
发明人： NAKAMURA KATSUSHI , KITAGAWA AKIHIRO
IPC分类号： G11C27/02
摘要： PURPOSE:To avoid the restriction of the speeding-up of the whole of a circuit by, for example, connecting outputs of first stages of a two stage type operational amplifier with prescribed voltages via analog switches and initializing output voltages held on Miller phase compensation capacitances at the time of resetting a sample-hold circuit. CONSTITUTION:Input analog signals from terminals 3, 4 arc sampled on capacitances C1, C2 with a clock theta1 via analog switches S4, S5 and terminals 7 to 12 are connected to a grounding terminal 2 by S6 to S11 and then the sample-hold circuit is reset. At the time of a holding, S6 to S11 are turned OFF with theta2 and the reset is released and S1 to S3 are turned ON. Then, input signals held on C1, C2 are shifted to C3, C4 and voltages of signals are amplified by the ratio of respective capacitances to be outputted to terminals 9, 10. Further, since an initializing circuit 15 is connected through terminals 13, 14 and via S12 with theta1, a resetting time is shortened without increasing the stationary current of the operational amplifier.

10. 发明专利

JPH07142682A RESISTANCE CIRCUIT 失效
公开(公告)号：JPH07142682A
公开(公告)日：1995-06-02
申请号：JP28795793
申请日：1993-11-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMAMOTO ETSUJI , KITAGAWA AKIHIRO
IPC分类号： H01L21/822 , H01L27/04 , H03M1/34 , H03M1/76
摘要： PURPOSE:To prevent a turnup part from being unmatched without forming a saw-toothed wiring by a method wherein resistors in a resistor array are connected together with a resistor of the same pattern of layout with a resistor provided at the turnup part to constitute a resistance circuit. CONSTITUTION:Arranged resistors each provided with resistor terminals 1a and 1b and a resistor layer 2 are linked together with linking wirings 3 formed of aluminum wiring low in resistance to constitute two arrays of resistors. The two arrays of resistors are connected together with a turnup part wirings 4 which is formed of aluminum wiring low in resistance and of the same pattern of layout with the linking wiring 3. By this setup, a resistor voltage-dividing circuit can be very accurately integrated and lessened in chip area without forming a saw-toothed wiring.

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