会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 22. 发明专利
    • PULSE GENERATING CIRCUIT
    • JP2000201057A
    • 2000-07-18
    • JP213099
    • 1999-01-07
    • NIPPON ELECTRIC IC MICROCOMPUT
    • MARUYAMA SHIGERU
    • H03K3/033H03K3/355H03K5/14H03L7/24
    • PROBLEM TO BE SOLVED: To provide a pulse generating circuit for generating a stable pulse. SOLUTION: This pulse generating circuit is constituted of an OS(oscillator) circuit 1 for inputting a clock signal, a P channel MOS transistor 2 for receiving the output of the OS circuit at the gate, a delay circuit 4 connected with an output line 10, an OS circuit 5 for inputting the output of the delay circuit, an N channel MOS transistor 3 for receiving the output of the OS circuit at the gate, an inverter 6 for outputting the anti-phase of the output of the OS circuit, a delay circuit 7 connected with the output line 10, an AND circuit 8 for inputting the outputs of the inverter 6 and the delay circuit 7, and an N channel MOS transistor 9 for receiving the output of the AND circuit at the gate. When a clock signal is changed from a low level to a high level in a period in which an output is a high level in an initial state, the output level of the delay circuit 7 connected with the output line 10 is turned into a high level, and the output of the inverter 6 is also turned into a high level. Then, the N channel MOS transistor 9 is turned on by the AND circuit 8, and the output level is changed to a low level.
    • 23. 发明专利
    • SYNCHRONIZED SIGNAL OSCILLATING CIRCUIT
    • JP2000091909A
    • 2000-03-31
    • JP25722998
    • 1998-09-10
    • SHARP KK
    • MORI HARUYA
    • H03K4/06H03K3/0231H03K4/502H03L7/00H03L7/06H03L7/24
    • PROBLEM TO BE SOLVED: To provide the synchronized signal oscillating circuit where a period and an amplitude of its oscillated output are made constant during a self-running oscillation and a synchronized oscillation so that the oscillated output is quickly synchronized with a synchronizing pulse in the case of shifting from the self- running oscillation state to the synchronized oscillation state, the oscillated output is not lowered than a specified lower limit, fluctuation in the oscillated amplitude is suppressed, and the self-running oscillation state is smoothly shifted from the synchronized oscillation state after missing the synchronizing pulse so as to realize the stable oscillation period and the stable oscillation amplitude. SOLUTION: An invalidating means 17 inhibits the output as of either of a 1st comparison means 14 or a 2nd comparison means 15 from being transmitted to a state maintenance means 16 when a synchronizing pulse is in an active state permits the transmission of the output to the means 16 when the synchronizing pulse is an inactive state on the other hand. Furthermore, when the synchronizing pulse shifts to the inactive state, an edge trigger means 18 switches over the output signal of the state maintenance means 16 between a lowering signal and an ascending signal.
    • 24. 发明专利
    • INJECTION SYNCHRONIZED OSCILLATOR
    • JPH09162733A
    • 1997-06-20
    • JP34510395
    • 1995-12-08
    • NIPPON TELEGRAPH & TELEPHONE
    • KAMOGAWA KENJITOKUMITSU TSUNEO
    • H03L7/24
    • PROBLEM TO BE SOLVED: To expand the upper frequency limit of oscillator by increasing feedback quantity by interposing an impedance transformer in the connection of feedback circuit through an irreversible distributing/synthesizing circuit. SOLUTION: An irreversible distributing/synthesizing circuit 10 distributes both the input signals of terminals 11 and 12 to terminals 13 and 14 but there is no signal transmission between the terminals 11 and 12 and between the terminals 13 and 14. An amplifier 20 connects its output terminal 22 and input terminal 21 to a loop while using the path from the terminal 11 of irreversible distributing/synthesizing circuit 10 to the terminal 13 as the feedback circuit and free oscillation is generated within the prescribed range of loop gain and phase turn. In this case, an impedance transformer 40 composed of the low impedance line of 20, for example, is inserted between the terminal 13 and the terminal 21. Thus, impedance matching at a terminal 13a is attained, the characteristics of distribution from the terminal 12 to the terminal 21 are improved, and the gain reduction of amplifier 20 at high frequency is compensated.