专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2000196572A BIT PHASE CONTROLLER 失效
公开(公告)号：JP2000196572A
公开(公告)日：2000-07-14
申请号：JP36840498
申请日：1998-12-25
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUMOTO SHUICHI , YAMAOKA SHINSUKE
IPC分类号： H03L7/00 , H04L1/22 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To reduce a quantity of aborted data until phase locking is established by reducing a control time to set up accurate phase locking. SOLUTION: A main count γ is set to a main counter 11 as an initial delay and the operation is started. Simultaneously, a sub count χ is set to a sub counter 12. A plus.minus computing element 14 is used to increase the count χwhile selecting alternately γ+χ and γ-χ, centered at the main count γ, for a phase difference of standby system data with respect to active system data. A phase change in the active system data with respect to a clock signal is monitored through the operation above. When any phase change is detected, the main count γ is changed to maintain the phase difference of the active system data with respect to the clock signal.

2. 发明专利

JPH114219A VOLTAGE-CONTROLLED DELAY CIRCUIT, DIRECT PHASE CONTROL TYPE VOLTAGE-CONTROLLED OSCILLATOR, CLOCK/DATA REPRODUCING CIRCUIT AND CLOCK/DATA REPRODUCING DEVICE 失效
公开(公告)号：JPH114219A
公开(公告)日：1999-01-06
申请号：JP15651597
申请日：1997-06-13
申请人： OKI ELECTRIC IND CO LTD
发明人： YAMAOKA SHINSUKE
IPC分类号： H03K3/354 , H03K5/00 , H03K5/13 , H03L7/07 , H03L7/081 , H03L7/099 , H04L7/02 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To form a satisfactorily sinchronized clock by executing a propagation processing with the processing delayed amount corresponding to a delay control voltage signal and inputting a clock from outside to a voltage control logical gate at a position corresponding to a clock phase selection signal from outside by way of a clock introduction logical gate controlled to be through condition by the clock phase selection signal from outside. SOLUTION: A clock phase selection signal given by a control circuit 2-1-3 to a voltage control delay circuit 2-1-1 has only one bit out of five bits at an H level in a steady state. In the voltage control delay circuit 2-1-1, only an AND gate to which a clock phase selection signal bit at the H level is inputted opens and an input clock is introduced to a cascade continuation system of a voltage control delay NOR gate. The inputted clock propagates the voltage control type delay NOR gate at a post stage and a delayed phase clock is outputted from the voltage control type delay NOR gate. The control circuit 2-1-3 operates at an inversion clock of the input clock.

3. 发明专利

JPH0983499A BIT PHASE SYNCHRONOUS CIRCUIT, BIT PHASE SYNCHRONIZING DEVICE AND DATA LATCH TIMING DECISION CIRCUIT 失效
公开(公告)号：JPH0983499A
公开(公告)日：1997-03-28
申请号：JP22994995
申请日：1995-09-07
申请人： OKI ELECTRIC IND CO LTD
发明人： YAMAOKA SHINSUKE , YOSHIDA SATOSHI , MATSUMOTO SHUICHI , TAYA TAKASHI
IPC分类号： H03K5/00 , H04L7/00 , H04L7/02 , H04L25/40
摘要： PROBLEM TO BE SOLVED: To stably output data latched in a most proper timing with respect to data and a clock signal whose mutual phase relation is unknown. SOLUTION: A pulse width generating circuit 1 makes a pulse width of input data of an NRZ signal from a data input terminal 0 narrow and provides an output of a 1st pulse width signal, a 2nd pulse width signal and delayed data delaying input data by a prescribed time. Even when mutual phase relation between the input data and n-phases clocks ϕ1 to ϕn being 1/n equal divisions of one clock width of the input data is unknown, shift registers 41 to 4n are used to match the top and the tail end to absorb phase fluctuation in m-bit width and data latched and outputted by latch timing decesion circuits 21 to 2n and phase align circuits 31 to 3n in the most proper timing are outputted stably from a selector 6 synchronously with the clock ϕ1.

4. 发明专利

JPH06343059A OPTICAL FIBER PARALLEL TYPE TRANSMITTING DEVICE 失效
公开(公告)号：JPH06343059A
公开(公告)日：1994-12-13
申请号：JP13062193
申请日：1993-06-01
申请人： OKI ELECTRIC IND CO LTD
发明人： YOSHIDA SATOSHI , TAYA TAKASHI , YAMAOKA SHINSUKE
IPC分类号： H04B10/25 , H04B10/00 , H04B10/293 , H04B10/564 , H04B10/572 , H04B10/04 , H04B10/12
摘要： PURPOSE:To economically shape the waveform in each optical fiber without using any monitor line that is exclusively used for setting the threshold value by using one of those signals obtained by applying the photoelectric conversion to the outputs of plural optical fibers for detection of the threshold value and then using the detection output as the threshold value of each comparator. CONSTITUTION:A photoelectric converter 4 converts the optical signal 1-n of an optical fiber 1 into electric signals via an optical input terminal 3 of a receiving optical device 2. These electric signals are supplied to the input terminals A of comparators 5. The output of a converter 4 (n) is supplied to a threshold value detecting circuit 6, and the detection output of the circuit 6 is supplied to each input terminal B as the threshold value signal of each comparator 5. Then each comparator 5 decides the logical value of the input electric signal of the terminal A based on the input threshold value signal of the terminal B and then performs the waveform shaping. Furthermore the circuit 6 can easily detect the threshold value of the input optical signal of the converter 4(n) since this signal has its mark rate of about 0.5 and also a satisfactorily high quenching ratio. Thus the economical waveform shaping is attained without using any monitor line exclusive for setting the threshold value nor a light emitter and a light receiver.

5. 发明专利

JPH11317732A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH11317732A
公开(公告)日：1999-11-16
申请号：JP36271798
申请日：1998-12-21
申请人： OKI ELECTRIC IND CO LTD
发明人： YAMAOKA SHINSUKE , TAYA TAKASHI , YOSHIDA SATOSHI , MATSUMOTO SHUICHI
IPC分类号： H04J3/06 , H04L7/033 , H04L7/10 , H04L25/40 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To provide a bit phase synchronizing circuit which obtain stricter bit phase synchronism with burst data than that of continuous transmission data in very short cycles. SOLUTION: A stable phase selecting circuit 16 after fetching a reset signal from a reset signal input terminal 17 fetches burst cell data from a data input terminal 7, detects a preamble PR where the synchronous pattern of the head part of the burst cell data is arranged by using polyphase clocks 1 to n to detect the timing of a stable phase early, and outputs data and a clock synchronized with the input burst cell data. For the synchronizing data, three pieces of data including data of the stablest adjacent phases are outputted together as data outputs 1 to 3 and supplied to a timing decision circuit 5 and the data output 2 of the stablest phase is supplied to a data output terminal 8. A stable phase selecting circuit 16 supplies the synchronizing clock to a clock output terminal 9 as well.

6. 发明专利

JPH10145344A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH10145344A
公开(公告)日：1998-05-29
申请号：JP30206196
申请日：1996-11-13
申请人： OKI ELECTRIC IND CO LTD
发明人： YOSHIDA SATOSHI , TAYA TAKASHI , YAMAOKA SHINSUKE
IPC分类号： H04L1/22 , H04L7/00 , H04L7/02
摘要： PROBLEM TO BE SOLVED: To follow up a phase in wide range with respect to the phase fluctuation of an input signal by providing a means for selecting one of plural systems of phase synchronizing means and serial-parallel conversion means, and a means for switching these systems. SOLUTION: Two phase synchronizing circuits consisting of phase judging circuits 101 and 102, control circuits 111 and 112, and a variable delay circuit 120 follow up the phase of a delay clock with respect to the input signal whose phase fluctuates hourly. A synchronizing pattern detecting circuit 13X (X is 1 or 2) detects the synchronizing pattern of a transferring signal, and a serial- parallel conversion circuit 14X divides the frequency of the delay clock outputted from the circuit 120 to generate a slow clock and makes an input signal a parallel signal synchronizing with the slow clock to output. A system selection control circuit 150 outputs a switching signal for switching a nonselected system to a selected system to a system selecting circuit 151 at the time of recognizing that the failure of the phase following up of the selected system is near, from the output signals of the circuits 111 and 112 and the outputs of the circuits 101 and 102.

7. 发明专利

JPH0744473A SIGNAL TRANSMISSION RECEPTION CIRCUIT 失效
公开(公告)号：JPH0744473A
公开(公告)日：1995-02-14
申请号：JP18959493
申请日：1993-07-30
申请人： OKI ELECTRIC IND CO LTD
发明人： TAYA TAKASHI , YAMAOKA SHINSUKE
IPC分类号： G06F13/00
摘要： PURPOSE:To send/receive plural signals between a sender side circuit and a receiver side circuit in parallel with a few signal lines with almost immunity to noise effect. CONSTITUTION:Output drive circuits 4-7 in a sender side circuit 1 drive corresponding signal lines 22-25 in response to received signals A-D and a reference voltage generating circuit 3 generates a reference voltage with a predetermined voltage relation to a signal voltage from each output drive circuit to provide an output to a signal line 26. Each of voltage comparators 8-11 of a receiver side circuit 2 compares a reference voltage from a certain signal line with a signal voltage from a signal line connecting to a corresponding output drive circuit and regenerate signals E-H inputted to the corresponding output drive circuit.

8. 发明专利

JPH06303133A OSCILLATION CIRCUIT, FREQUENCY VOLTAGE CONVERSION CIRCUIT, PHASE LOCKED LOOP CIRCUIT AND CLOCK EXTRACT CIRCUIT 失效
公开(公告)号：JPH06303133A
公开(公告)日：1994-10-28
申请号：JP9117993
申请日：1993-04-19
申请人： OKI ELECTRIC IND CO LTD
发明人： TAYA TAKASHI , YOSHIDA SATOSHI , YAMAOKA SHINSUKE , ODAGIRI HIDEAKI
IPC分类号： H03L7/097 , H04L7/02 , H04L7/033
摘要： PURPOSE:To allow the oscillation circuit, the frequency voltage conversion circuit, the phase locked loop circuit and the clock extract circuit to be suitable for circuit integration by improving tracking performance of input data regardless of their small size. CONSTITUTION:An output of a voltage controlled oscillator circuit 4 is inputted to a frequency voltage conversion circuit 1, and a voltage difference between an output of the frequency voltage conversion circuit 1 and an output voltage of a reference frequency voltage converter 2 is fed to a control voltage of the voltage controlled oscillator circuit 4. Thus, the frequency accuracy of the oscillation circuit is easily improved in the integrated circuit, a defect of difficulty in the circuit integration and the need of adjustment of the voltage controlled oscillator circuit 4 is eliminated and defects of the phase locked loop circuit and the clock extract circuit such as large sized components or a long time from impression of an input signal till output of an extracted clock are avoided.

9. 发明专利

JPH05227145A CLOCK OSCILLATION CIRCUIT AND CLOCK EXTRACTION CIRCUIT 失效
公开(公告)号：JPH05227145A
公开(公告)日：1993-09-03
申请号：JP2362892
申请日：1992-02-10
申请人： OKI ELECTRIC IND CO LTD
发明人： TAYA TAKASHI , YOSHIDA SATOSHI , YAMAOKA SHINSUKE , ODAGIRI HIDEAKI
IPC分类号： H03K5/00 , H03K3/282 , H03L7/00 , H04J3/06 , H04L7/033
摘要： PURPOSE:To output a clock signal whose phase is synchronized with that of an input signal for oscillation phase control that is inputted by controlling a self-running oscillation phase corresponding to the input signal for oscillation phase control. CONSTITUTION:An emitter-coupled multivibrator circuit 11 performs self-running oscillation simultaneously with the supply of a power source. Meanwhile, a driver circuit 10 fetches a pulse signal for oscillation phase control, and detects whether or not it exceeds a threshold value, and such detection signal is supplied to one terminal of a timing capacitor C1 via a diode D3, and when it is judged that it exceeds the threshold value, the detection signal is used for control to lead or lag the oscillation phase, and when it is less than the threshold value. no change control of the self-running oscillation phase is performed. In such a way, the clock signal can be outputted by performing the self-running oscillation simultaneously with the supply of the power source, and also. the self- running oscillation phase can be controlled corresponding to, for example, a pulse rise or fall timing.

10. 发明专利

JP2000049760A BIT PHASE CONTROLLER 失效
公开(公告)号：JP2000049760A
公开(公告)日：2000-02-18
申请号：JP21355998
申请日：1998-07-29
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUMOTO SHUICHI , YAMAOKA SHINSUKE
IPC分类号： H04L7/00 , H04L7/02
摘要： PROBLEM TO BE SOLVED: To shorten control time for establishing accurate phase synchronization and to reduce data amount which is to be abandoned until the phase synchronization is established. SOLUTION: A main count value γ is set to a main counter 11 as the initial value to a delay amount, and operation is started. At the same time, a sub count value χ is set to a sub counter 12. By using a addition/subtracting computing element 14, χ is increased while alternately switching the phase difference of standby system data to active system data to γ+χ and γ-χ with the main count value as a center. With this operation, the phase change in the active system data to clock signals is monitored. When the phase change is detected, the main count value γ is changed, and the phase difference of the active system data to the clock signals is maintained.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式