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21. 发明专利

JP5433614B2 Semiconductor integrated circuit and the receiving device 有权
公开(公告)号：JP5433614B2
公开(公告)日：2014-03-05
申请号：JP2011064572
申请日：2011-03-23
申请人：株式会社東芝
发明人：田翔子織 , 口淳出
IPC分类号： H03F3/195 , H03F1/56 , H04B1/16 , H04B1/18
CPC分类号： H04B1/16

22. 发明专利

JP2014030197A Cmos transceiver having integrated power amplifier 有权
标题翻译：具有集成功率放大器的CMOS收发器
公开(公告)号：JP2014030197A
公开(公告)日：2014-02-13
申请号：JP2013162804
申请日：2013-08-05
申请人： Qualcomm Incorporated , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： DAVID J WEAVER , PATRIK YUE , DAVID SUE
IPC分类号： H03F1/52 , H01L21/8234 , H01L23/66 , H01L27/06 , H01L27/088 , H03F1/22 , H03F3/195 , H03F3/24 , H03F3/45 , H04B1/04
CPC分类号： H01L24/06 , H01L23/66 , H01L24/48 , H01L24/49 , H01L27/088 , H01L2223/6644 , H01L2224/05554 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01031 , H01L2924/01051 , H01L2924/01052 , H01L2924/10329 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H03F1/223 , H03F3/24 , H03F3/45188 , H03F2200/06 , H03F2203/45638 , H03F2203/45652 , H04B2001/0408 , Y10S977/724 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a breakdown resistant transistor structure for amplifying communication signals.SOLUTION: This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving an input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to a drain of the first NMOS transistor, a gate connected to a reference DC voltage, a drain that provides an output of an amplified radio signal, and a load disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator. The second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith. The second insulator is thicker than the first insulator.
摘要翻译：要解决的问题：提供用于放大通信信号的耐击穿晶体管结构。解决方案：该结构包括具有连接到地的源极的第一NMOS晶体管和用于接收输入射频信号的第一栅极。第一栅极设置在第一绝缘体之上，并且第一NMOS晶体管具有与之相关联的第一跨导和第一击穿电压。还包括第二NMOS晶体管，其源极连接到第一NMOS晶体管的漏极，连接到参考DC电压的栅极，提供放大的无线电信号的输出的漏极和设置在参考DC电压之间的负载和第二NMOS晶体管的漏极。第二栅极设置在第二绝缘体上方。第二NMOS晶体管具有与之相关联的第二跨导和第二击穿电压。第二绝缘体比第一绝缘体厚。

24. 发明专利

JP5349666B2 Metal oxide semiconductor devices with an integrated bias circuit 有权
公开(公告)号：JP5349666B2
公开(公告)日：2013-11-20
申请号：JP2012223941
申请日：2012-10-09
申请人：アギアシステムズインコーポレーテッド
发明人：ロペツオズヴァルド , モリソンロットジョエル
IPC分类号： H01L21/822 , H03F1/30 , G05F3/20 , H01L27/04 , H03F3/195
CPC分类号： H03F3/195 , G05F3/205 , H01L2224/49175 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F1/301 , H03F2200/18 , H01L2924/00
摘要： An IC device includes an MOS device having a gate terminal, a source terminal and a drain terminal, the gate terminal being operatively coupled to an input of the IC device, the drain terminal being operatively coupled to an output of the IC device, and the source terminal being coupled to a negative voltage supply. The IC device further includes a bias generator operatively coupled to the gate terminal of the MOS device, the bias generator generating a bias voltage and/or a bias current for biasing the MOS device at a substantially constant quiescent operating point. The bias generator is configured such that the bias voltage and/or bias current varies as a function of a junction temperature of the MOS device. In this manner, the bias generator accurately tracks one or more operating conditions of the MOS device, thereby improving the performance of the device.

25. 发明专利

JP2013165446A High-frequency power amplifier circuit and radio communication apparatus 审中-公开
标题翻译：高频功率放大器电路和无线电通信设备
公开(公告)号：JP2013165446A
公开(公告)日：2013-08-22
申请号：JP2012028644
申请日：2012-02-13
申请人： Sharp Corp , シャープ株式会社
发明人： TAWARA KENJI , YAMAMOTO RYOTARO , KANI HIROYUKI , TOMONARI DAISUKE
IPC分类号： H03F1/02 , H03F3/195 , H03F3/24 , H03F3/68
摘要： PROBLEM TO BE SOLVED: To achieve higher efficiency and improvement in packaging density in a substrate.SOLUTION: A high-frequency power amplifier circuit comprises: a resistor RL which is a fixed impedance and connected to a collector terminal 4c side; a base terminal 3b connected to a base terminal 2b side; a base terminal 4b connected to the base terminal 2b side and the base terminal 3b side; and a collector terminal 3c connected to a collector terminal 2c side. The collector terminal 4c is not connected to both of the collector terminal 2c side and the collector terminal 3c side.
摘要翻译：要解决的问题：为了实现更高的效率和提高基板中的封装密度。解决方案：高频功率放大器电路包括：固定阻抗并连接到集电极端子4c侧的电阻器RL; 连接到基端子2b侧的基端子3b; 连接到基端子2b侧和基端子3b侧的基极端子4b; 以及与集电极端子2c侧连接的集电极端子3c。集电端子4c不与集电端子2c侧和集电端子3c侧连接。

26. 发明专利

JP2013131994A Radio communication apparatus 有权
标题翻译：无线电通信设备
公开(公告)号：JP2013131994A
公开(公告)日：2013-07-04
申请号：JP2011281659
申请日：2011-12-22
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： HAGISAWA HIROSHI , SAKURAI SATOSHI
IPC分类号： H03F3/24 , H03F3/193 , H03F3/195
CPC分类号： H04W52/028 , Y02D70/00 , Y02D70/1262
摘要： PROBLEM TO BE SOLVED: To provide a radio communication apparatus that implements improved transmission power characteristics or reduced resources required to improve transmission power characteristics.SOLUTION: The radio communication apparatus includes, for example, a bias detection circuit SENS for detecting a bias supplied to a high frequency power amplifier HPA; an error amplifier EAb for amplifying an error between the detection result and a predetermined reference voltage Vref; and a correction circuit CC for searching for a bit correction value ΔBC that minimizes the error detected by EAb. During a normal operation, a digital-analog conversion circuit DAC receives a bias instruction code VBCD from a baseband unit BBU, and reflects ΔBC in VBCD for outputting a bias setting voltage Vb, so that a corresponding bias is supplied to HPA.
摘要翻译：要解决的问题：提供一种实现改善发射功率特性或降低发射功率特性所需的资源的无线电通信装置。解决方案：无线电通信装置包括例如偏置检测电路SENS，用于检测提供给高频功率放大器HPA; 误差放大器EAb，用于放大检测结果与预定参考电压Vref之间的误差; 以及用于搜索最小化由EAb检测到的误差的位校正值＆amp; Dgr; BC的校正电路CC。在正常操作期间，数模转换电路DAC从基带单元BBU接收偏置指令代码VBCD，并且在VBCD中反映并输出偏差设定电压Vb的Dgr; BC，从而向HPA提供相应的偏置。

27. 发明专利

JP2013522955A Laminated double inductor structure 有权
公开(公告)号：JP2013522955A
公开(公告)日：2013-06-13
申请号：JP2012557028
申请日：2010-11-08
申请人：ザイリンクスインコーポレイテッドXilinx Incorporated
发明人：キレエフ，バシリ
IPC分类号： H03F3/195
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要：二重インダクタ構造（１００）は、第１の複数のコイル（２０５−２２０）を含む第１のインダクタ（１１０）を含み得る。第１の複数のコイルのうちの各々のコイルは、複数の導電層（１０５，２５５−２６０）のうちの異なる導電層内に配置され得る。第１の複数のコイルの内のコイルは、垂直方向に積層されるとともに垂直軸に対して同心であり得る。二重インダクタ構造は、第２の複数のコイル（４０５−４２０）を含む第２のインダクタ（１１５）をさらに含み得る。第２の複数のコイルの各々は、複数の導電層のうちの異なる導電層内に配置され得る。第２の複数のコイルのうちのコイルは、垂直方向に積層されるとともに垂直軸に対して同心であり得る。各々の導電層内において、第２の複数のコイルのうちのあるコイルは、第１の複数のコイルのうちのあるコイルの内側の周辺に配置され得る。

28. 发明专利

JP2013009440A Metal oxide semiconductor device having integrated bias circuit 有权
标题翻译：具有集成偏置电路的金属氧化物半导体器件
公开(公告)号：JP2013009440A
公开(公告)日：2013-01-10
申请号：JP2012223941
申请日：2012-10-09
申请人： Agere Systems Inc , アギアシステムズインコーポレーテッド
发明人： LOPEZ OSVALDO , LOTT JOEL M
IPC分类号： H01L21/822 , H03F1/30 , G05F3/20 , H01L27/04 , H03F3/195
CPC分类号： H03F3/195 , G05F3/205 , H01L2224/49175 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F1/301 , H03F2200/18 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide techniques capable of accurately compensating for variations in a bias condition of a MOS device resulting from temperature and/or process variations of the device.SOLUTION: An IC device includes a MOS device having a gate terminal, a source terminal, and a drain terminal. The gate terminal is operatively coupled to an input of the IC device, the drain terminal is operatively coupled to an output of the IC device, and the source terminal is coupled to a negative voltage supply. The IC device further includes a bias generator which is operatively coupled to the gate terminal of the MOS device and generates a bias voltage and/or a bias current for biasing the MOS device at a substantially constant quiescent operating point. The bias generator is configured such that the bias voltage and/or bias current varies as a function of a junction temperature of the MOS device. In this manner, the bias generator accurately tracks one or more operating conditions of the MOS device, thereby improving the performance of the device.
摘要翻译：要解决的问题：提供能够精确补偿由器件的温度和/或工艺变化导致的MOS器件的偏置状态的变化的技术。解决方案：IC器件包括具有栅极端子，源极端子和漏极端子的MOS器件。栅极端子可操作地耦合到IC器件的输入，漏极端子可操作地耦合到IC器件的输出，源极端子耦合到负电压源。 IC器件还包括偏置发生器，其可操作地耦合到MOS器件的栅极端子，并产生偏置电压和/或偏置电流，用于在基本上恒定的静态工作点处偏置MOS器件。偏置发生器被配置为使得偏置电压和/或偏置电流作为MOS器件的结温的函数而变化。以这种方式，偏置发生器精确地跟踪MOS器件的一个或多个工作条件，从而提高器件的性能。版权所有（C）2013，JPO＆INPIT

29. 发明专利

JP2012509033A Ip2 rf transceiver ic having an internal loopback conductor for the self-test 有权
公开(公告)号：JP2012509033A
公开(公告)日：2012-04-12
申请号：JP2011536534
申请日：2009-11-13
申请人：クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人：アーラリ、バーマン , コ、ジン−ス , コールマン、ミヒャエル
IPC分类号： H04B1/40 , H03F3/195
CPC分类号： H04B1/40 , H03D7/168
摘要：【解決手段】ＲＦ送受信機集積回路は、ＩＰ２セルフテスト及び／またはキャリブレーションを行うのに使用出来る新規なセグメント化された低寄生容量の内部ループバック導電体を有する。第１の新規な側面では、送受信機の送信ミキサは電流モード出力ミキサである。受信ミキサは、低入力インピーダンスを有するパッシブミキサである。ループバックモードでは、送信ミキサは２つのトーン電流信号を、ループバック導電体を介してパッシブミキサに駆動する。第２の新規な側面では、送信ミキサの１つの直交位相分岐のみが、ＩＰ２テストを実行するのに必要な両トーンを生成するために使用される。第３の新規な側面では、第１のキャリブレーションテストが、送信ミキサの１つの直交位相分岐を用いて実行され、これは第２のキャリブレーションテストが他の直交位相分岐を用いて実行されるのと同時に行われ、これによりループバックテスト時間及び電力消費が低減される。
【選択図】図２

30. 发明专利

JP2012075178A Transistor amplifier having reduced parasitic oscillation 有权
标题翻译：具有减少的PARASITIC振荡的晶体管放大器
公开(公告)号：JP2012075178A
公开(公告)日：2012-04-12
申请号：JP2011266764
申请日：2011-12-06
申请人： Raytheon Co , レイセオンカンパニー
发明人： DOUGLAS A TEETER , PLATICAR ARIE
IPC分类号： H03F3/21 , H03F1/08 , H03F3/195 , H03F3/68
CPC分类号： H03F1/083 , H03F3/195 , H03F3/211 , H03F2200/366 , H03F2200/75
摘要： PROBLEM TO BE SOLVED: To provide a transistor amplifier having reduced parasitic, or parametric, oscillations.SOLUTION: A transistor device 12" having a plurality of transistor cells 15" includes a plurality of filters 18". Each one of the filters is coupled between an input node 20" and a corresponding one of control electrodes 17 of the plurality of transistor cells. A semiconductor provides a common active region for the plurality of transistor cells. Each one of the filters comprises: a conductive layer; a dielectric layer disposed on the conductive layer; a resistive layer disposed over the dielectric layer; a conductive electrode disposed in electrical contact with a first portion of the resistive layer and providing the input node; and a connector in electrical contact with a second portion of the resistive layer displaced from the first portion of the resistive layer which passes through the dielectric and is in electrical contact with the first conductor.
摘要翻译：要解决的问题：提供具有减小的寄生或参数振荡的晶体管放大器。解决方案：具有多个晶体管单元15“的晶体管器件12”包括多个滤波器18“，每个滤波器耦合在输入节点20”和多个控制电极17中的相应一个控制电极17之间的晶体管单元。半导体为多个晶体管单元提供公共有源区。每个滤波器包括：导电层; 布置在所述导电层上的电介质层; 设置在电介质层上的电阻层; 导电电极，设置成与所述电阻层的第一部分电接触并提供所述输入节点; 以及与电阻层的第二部分电接触的连接器，该第二部分从电阻层的穿过电介质的第一部分偏离并与第一导体电接触。版权所有（C）2012，JPO＆INPIT

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