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    • 22. 发明专利
    • Pass timing detecting method, pass timing detector and adaptive array antenna system
    • 通过时序检测方法,通过定时检测器和自适应阵列天线系统
    • JP2003338776A
    • 2003-11-28
    • JP2002146813
    • 2002-05-21
    • Nec Corp日本電気株式会社
    • YOSHIDA NAOMASA
    • H04B1/707H04B1/7113H04B1/7117H04B1/712H04B7/08H04B7/26H04W16/28H04W56/00H04W76/02H04Q7/38
    • H04B7/0897H04B1/7095H04B1/7113H04B1/7117H04B7/0842
    • PROBLEM TO BE SOLVED: To simplify a pass timing detection process to achieve superior detection characteristics.
      SOLUTION: A signal is despread over a plurality of chip timings for every antenna. A despread signal series for every antenna is received with a multi- beam to output a signal series for every beam and generate a delayed profile for every beam averaged over a constant period. A plurality of pass timings are detected in a process of selecting high-level chip timings one after another from the delayed profiles of all beams, without selecting those chip timings of less than a minimum selection timing interval centering around already selected chip timings in the following pass timing detection, and without selecting those chip timings of less than a minimum selection timing interval centering around beams of already selected chip timings with beams of less than a minimum selecting beam interval in the following pass timing detection.
      COPYRIGHT: (C)2004,JPO
    • 要解决的问题:为了简化通过时间检测处理以实现优异的检测特性。 解决方案:在每个天线的多个芯片定时上对信号进行解扩。 用多波束接收每个天线的解扩信号序列,以输出每个波束的信号序列,并为恒定周期中平均的每个波束生成延迟的分布。 在从所有波束的延迟分布中选择高电平芯片定时的过程中检测到多个通过定时,而不选择在下面的已经选择的芯片定时周围的小于最小选择定时间隔的那些芯片定时 并且在下面的通过定时检测中,不选择以具有小于最小选择波束间隔的波束的已经选择的芯片定时的波束的小于最小选择定时间隔的那些芯片定时。 版权所有(C)2004,JPO
    • 27. 发明专利
    • Wireless communication system
    • 无线通信系统
    • JP2010011061A
    • 2010-01-14
    • JP2008167707
    • 2008-06-26
    • Denso CorpNippon Soken Inc株式会社デンソー株式会社日本自動車部品総合研究所
    • MITSUHARU KENICHIROTAKAOKA AKIRANAITO HIROMICHI
    • H04B1/707B60R25/01B60R25/24E05B49/00H04B1/3822H04B1/40H04B1/7075H04B17/00H04W4/04H04W88/02
    • H04B1/7093G07C2009/00793G07C2209/06H04B1/7077H04B1/7095H04B2201/70711H04B2201/70715
    • PROBLEM TO BE SOLVED: To provide a wireless communication system which shortens time required for synchronous acquisition rather than in the prior art to improve responsiveness when communication is performed by a spread spectrum system. SOLUTION: A sliding correlator (or matched filter) does not immediately start trial of the synchronous acquisition and waits for a synchronous point retrieval start control signal from a CPU even when it becomes a state in which the trial of the synchronous acquisition can be started at a point of time t2 by starting reception of an actual receiving signal at a point of time t1 by an onboard unit for RF reception. Then, when the synchronous point retrieval start control signal comes at a point of time t3, to a point of time t4 when the synchronous point retrieval end control signal comes is used as a retrieval period, and the trial of the synchronous acquisition is started for a period where there is a starting point in the retrieval period. As a result, the synchronous acquisition is successful at a point of time t5 when the receiving signal using the time t3 as the starting point is received for one period, despreading demodulation is performed after that. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种无线通信系统,其缩短了同步采集所需的时间,而不是在现有技术中,以便在由扩频系统执行通信时提高响应性。 解决方案:滑动相关器(或匹配滤波器)不会立即开始同步采集试验,并且等待来自CPU的同步点检索开始控制信号,即使当其成为同步采集的试验可以 通过在时间点t1开始接收实际接收信号,通过用于RF接收的车载单元在时间点t2开始。 然后,当同步点检索开始控制信号到达时间点t3时,当使用同步点检索结束控制信号作为检索周期时,到时间点t4,并且开始同步采集的试验 在检索期间有起点的时期。 结果,当以时间t3为起点的接收信号被接收一个周期时,在时间点t5的同步捕获成功,在此之后执行解扩解调。 版权所有(C)2010,JPO&INPIT
    • 30. 发明专利
    • Digital correlator
    • JP2005519563A
    • 2005-06-30
    • JP2003575526
    • 2003-03-12
    • 株式会社東芝
    • ルウイス、ジョナサン・デビッド
    • G06F17/15H03H17/02H04B1/707
    • H04B1/7093G06F17/15H03H17/0254H04B1/7095
    • 発明は一般に、スペクトル拡散受信器のための、特に第三世代(3G)移動通信システムのための改良された相関器に関連する。 複数の遅延構成があるゴレイ相関器が説明される。 これらの遅延構成の少なくとも1つは共通の入力バス(720)を共有する複数のメモリ要素(704)と、メモリ要素の各々について1つである、複数のビット位置(712)を有する巡回シフトレジスタ(610)とを含み、各ビット位置は単一ビットを記憶し、関連するビット位置出力(706)を有し、各ビット位置出力が活動的であるとき、メモリ要素にデータを書き込むことを可能にするために、各ビット位置出力が前記メモリ要素の対応する1つと結合され、使用中に、前記巡回シフトレジスタのビット位置の1つだけが活動的であり、活動的なビット位置は共通バスのデータが書き込まれるメモリ要素を選択するためにシフトレジスタを通して巡回的に移動する。 巡回シフトレジスタは2つ以上の遅延構成の間で共有されてもよい。