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21. 发明专利

JPS5726931A Programmable counter 失效
标题翻译：可编程计数器
公开(公告)号：JPS5726931A
公开(公告)日：1982-02-13
申请号：JP10147480
申请日：1980-07-24
申请人： Nec Corp
发明人： ICHIDA KENJI
IPC分类号： H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To avoid the speed characteristics with a special preset value, by providing a carry-out signal control circuit in a delay circuit of a carry-out signal. CONSTITUTION:A programmable counter 5-1 at high speed section detects ''4'' as carry-out value at all times, and the output of a carry-out circuit 5-3 is made to ''1'' and delay circuits 5-5, 5-6 are delayed by 2-bit. But, since a PE signal of a programmable counter 5-2 at low speed section, that is the output signal of RS-FF 5-8, controls a control circuit 5-9 consisting of logical product gate, the circuit 5-9 is set in the timing when a counter 5-2 is at ''0''. On the other hand, when ''4'' is used for the counter 5-1 and N2 (not equal to 0, integer value) is used for the counter 5-2, if the delay time of QD-QA-G from the rise edge of an input clock is within about 4 pulses of the input clock, no malfunction is taken place.
摘要翻译：目的：通过在进位信号的延迟电路中提供进位信号控制电路，以避免具有特殊预设值的速度特性。构成：高速部分的可编程计数器5-1始终将“4”作为进位值检测，进位电路5-3的输出为“1”，延迟电路 5-5，5-6被延迟2位。但是，由于低速部分的可编程计数器5-2（即RS-FF 5-8的输出信号）的PE信号控制由逻辑积门组成的控制电路5-9，电路5-9为在计数器5-2处于“0”的定时中设置。另一方面，当计数器5-1使用“4”，对于计数器5-2使用N2（不等于0，整数值）时，如果QD-QA-G的延迟时间来自输入时钟的上升沿在输入时钟的大约4个脉冲内，不会发生故障。

22. 发明专利

JP2005198339A Programmable frequency divider in phase lock loop 审中-公开
标题翻译：相位锁环中的可编程分频器
公开(公告)号：JP2005198339A
公开(公告)日：2005-07-21
申请号：JP2005041013
申请日：2005-02-17
申请人： Motorola Inc , モトローラ・インコーポレイテッドMotorola Incorporated
发明人： ATRISS AHMAD H , PETERSON BENJAMIN C , PARKER LANNY L
IPC分类号： H03K23/64 , H03K23/66 , H03L7/08 , H03L7/095 , H03L7/18
CPC分类号： H03K23/665 , H03L7/18 , Y10S331/02
摘要： PROBLEM TO BE SOLVED: To provide a programmable frequency divider for a phase lock loop having a latch circuit with a first input receiving a program integer and an output deriving a latch integer.
SOLUTION: A phase lock loop monitors a first digital signal and derives a second digital signal operating substantially at a frequency in-phase with the first digital signal. A programmable divider latches a program integer for deriving a latch integer, compares the latch integer to a certain integer, and derives a flag signal having a first state when the latch integer mismatches the certain integer or a flag signal having a second state when the latch integer matches the certain integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for deriving the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for deriving a lock detection signal.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有锁存电路的锁相环的可编程分频器，其具有接收程序整数的第一输入和导出锁存整数的输出。解决方案：锁相环监视第一数字信号并导出基本上以与第一数字信号同相的频率工作的第二数字信号。可编程分频器锁存用于导出锁存整数的程序整数，将锁存器整数与特定整数进行比较，当锁存器整数与某一整数失配或具有第二状态的标志信号时，导出具有第一状态的标志信号，整数与某个整数相匹配。当标志信号具有第一状态时，锁存整数递减。响应于第一和第二时钟信号延迟标志信号，以导出具有由程序整数确定的频率的第二数字信号。第一和第二数字信号被施加到用于导出锁定检测信号的锁定检测电路。版权所有（C）2005，JPO＆NCIPI

23. 发明专利

JP3503967B2 High-frequency programmable divider 失效
公开(公告)号：JP3503967B2
公开(公告)日：2004-03-08
申请号：JP25797693
申请日：1993-10-15
申请人：アジレント・テクノロジーズ・インク
发明人：ティモシー・エル・ヒルストロム
IPC分类号： H03K23/40 , H03K23/64 , H03K23/66
CPC分类号： H03K23/665

24. 实用新型

JPS6114203Y2 JPS6114203Y2 - 失效
公开(公告)号：JPS6114203Y2
公开(公告)日：1986-05-02
申请号：JP19325084
申请日：1984-12-20
IPC分类号： H03K21/00 , G11C19/28 , H03K23/50 , H03K23/66 , H03K23/54 , H03K23/40
CPC分类号： G11C19/28 , H03K23/502 , H03K23/665

25. 发明专利

JPS612912B2 JPS612912B2 - 失效
公开(公告)号：JPS612912B2
公开(公告)日：1986-01-28
申请号：JP13491281
申请日：1981-08-27
申请人： Matsushita Electric Ind Co Ltd
发明人： MIZUGUCHI HIROSHI
IPC分类号： G01R23/10 , G01R25/08 , H03K23/66
CPC分类号： H03K23/665

26. 发明专利

JPS5917726A Programmable frequency generator for inverter driving having inductive load 失效
标题翻译：用于具有感应负载的逆变器驱动的可编程频率发生器
公开(公告)号：JPS5917726A
公开(公告)日：1984-01-30
申请号：JP12810082
申请日：1982-07-21
申请人： Matsushita Electric Ind Co Ltd
发明人： DEGUCHI TAKASHI , EJIMA YASUYUKI , TADAMATSU HIDEKAZU
IPC分类号： G05B19/02 , H02M7/48 , H03K21/00 , H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To increase the number of degrees of freedom for frequency division ratio and reduce the burden of software, by using the frequency division due to a microcomputer for a relatively low-frequency part when a frequency is generated by a programmable frequency generator. CONSTITUTION:A frequency fOSC generated from a reference frequency oscillator 1 is inputted to a programmable counter 2, and the frequency which can be followed by a microcomputer 3 synthesized by the frequency division due to software of the microcomputer 3. The output of the programmable counter 2 is outputted directly to combine this frequency and a frequency range higher than this frequency, and the cascade connection circuit of the programmable counter 2 and a binary counter 4 is constituted equivalently, and a frequency to be applied to an inverter having an inductive load is synthesized. Consequently, the software frequency division ratio can be set to an optional integer to increase the number of degrees of freedom for frequency division ratio in comparison with the use of the binary counter, and a software timer is used only at the inverter start time to reduce the burden of software.
摘要翻译：目的：为了增加分频比的自由度数量，减少软件的负担，当由可编程频率发生器产生频率时，通过使用微机对相对低频部分的分频。构成：从参考频率振荡器1产生的频率fOSC被输入到可编程计数器2，并且由微计算机3的软件通过分频合成的微计算机3可以跟随的频率。可编程计数器的输出 2直接输出以组合该频率和高于该频率的频率范围，可编程计数器2和二进制计数器4的级联连接电路等效地构成，施加到具有感性负载的逆变器的频率为合成。因此，与使用二进制计数器相比，软件分频比可以设置为可选的整数，以增加分频比的自由度数，并且软件定时器仅在逆变器启动时间被使用以减少软件的负担。

27. 发明专利

JPS5915334A Programmable frequency generator 失效
标题翻译：可编程频率发生器
公开(公告)号：JPS5915334A
公开(公告)日：1984-01-26
申请号：JP12466082
申请日：1982-07-16
申请人： Matsushita Electric Ind Co Ltd
发明人： DEGUCHI TAKASHI , KAMIYAMA KAZUMI , TADAMATSU HIDEKAZU
IPC分类号： G05B19/02 , C08G2/04 , H02M7/48 , H03K21/00 , H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To change freely the frequency dividing ratio without increasing the number of component parts, by securing a part of a comparatively low frequency with division of a microcomputer MC. CONSTITUTION:A frequency fOSC generated from a reference frequency generator 1 is supplied to a CLK terminal of a programmable counter 2. The address codes are fed to address inputs P0-P7 from outputs O0-O7 of a microcomputer MC2. Thus the frequency dividing ratio is decided. The direct output of the counter 2 is set at f1 and then turned into an output f2 of a binary counter 4 which is incorporated into the counter 2. Then the output f2 is fed to an interruption input I0 of an MC3. An output f3 is obtained by dividing the output f2 with the software of the MC3. The final frequency output fOUT is delivered selectively via a selection output circuit 5 designated by output terminals O01- O03 of the MC3 and on the basis of a frequency range.
摘要翻译：目的：通过分配微型计算机MC，通过确保一部分较低频率，可以自由地改变分频比，而不增加组件数量。构成：从参考频率发生器1产生的频率fOSC被提供给可编程计数器2的CLK端。地址码从微型计算机MC2的输出O0-O7馈送到地址输入P0-P7。因此决定分频比。计数器2的直接输出被设置为f1，然后变成并入计数器2的二进制计数器4的输出f2。然后，输出f2被馈送到MC3的中断输入I0。通过将输出f2与MC3的软件分开来获得输出f3。最终频率输出fOUT通过由MC3的输出端子O01-003指定的选择输出电路5选择性地发送，并且基于频率范围。

28. 发明专利

JPS58182925A Programmable counter 失效
标题翻译：可编程计数器
公开(公告)号：JPS58182925A
公开(公告)日：1983-10-26
申请号：JP6541982
申请日：1982-04-21
申请人： Oki Electric Ind Co Ltd
发明人： SHIN YASUHIRO
IPC分类号： H03K23/58 , H03K23/00 , H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To obtain a maximum operation frequency for any program value, by inhibiting a read of a specific code detection signal in a section wherein a preset signal is generated. CONSTITUTION:In response to an input signal fIN, FFs f1-f8 count down and when an NOR gate 9 detects an output code being 4, the output of the gate G9 goes up to H. Its detection signal is delayed by shift registers S1-S3 to obtain the preset signal Y2, which is inputted to the reset input terminal R of the register S1. The register S1 does not read a signal inputted to an input terminal D9 while a level H is applied to the terminal R, and fixes the output terminal -09 at a level L. Consequently, even when preset data is 132, the register S1 does not read it even in case of a 4-detection error due to the H-level transfer delay of the most significant digit bit, so the data 132 is preset in the FFs f1-f8 normally, improving the highest operation frequency of the signal fIN.
摘要翻译：目的：为了获得任何程序值的最大操作频率，通过禁止在产生预置信号的部分中读取特定代码检测信号。构成：响应于输入信号fIN，FF f1-f8向下计数，当NOR门9检测到输出代码为4时，门G9的输出上升到H.它的检测信号被移位寄存器S1- S3以获得输入到寄存器S1的复位输入端子R的预设信号Y2。寄存器S1没有读取输入到输入端子D9的信号，而电平H被施加到端子R，并将输出端子-09固定在电平L.因此，即使预设数据是132，寄存器S1也是即使在由于最高有效位位的H电平传输延迟引起的4检测错误的情况下也不会读取它，因此数据132正常地预设在FF f1-f8中，从而提高信号fIN的最高工作频率。

29. 发明专利

JPS58178633A Programmable counter 失效
标题翻译：可编程计数器
公开(公告)号：JPS58178633A
公开(公告)日：1983-10-19
申请号：JP6087582
申请日：1982-04-14
申请人： Oki Electric Ind Co Ltd
发明人： SHIN YASUHIRO
IPC分类号： H03K23/58 , H03K23/00 , H03K23/66
CPC分类号： H03K23/665 , G05B2219/43008
摘要： PURPOSE:To prevent malfunction by suppressing the operation of a means to generate a preset signal obtained by decoding an output from a counter during the presetting of the counter. CONSTITUTION:A ripple carrier type programmable counter consisting of FF f1-f8 executes its counting operation by an input signal fIN, and when the counted value reaches a prescribed value, sends a signal X2 to a shift register F9. The shift register F9 delays the signal X2 by a prescribed time, sends a signal Y2 to a Prn among the Pr terminals of the FF f1-f8 and sets up the data of terminals D1-D8. Since the signal X2 is obtained by connecting OR circuits G6, G7, G8 and an NOR circuit G9 as shown in the figure in this invention, the signal X2 is not outputted during the output of the signal Y2, preventing the malfunction.
摘要翻译：目的：通过抑制在计数器预置期间通过解码来自计数器的输出而产生预置信号的装置的操作来防止故障。构成：由FF f1-f8组成的波纹载波型可编程计数器通过输入信号fIN执行其计数操作，当计数值达到规定值时，向移位寄存器F9发送信号X2。移位寄存器F9将信号X2延迟预定时间，向FF f1-f8的Pr端子中的Prn发送信号Y2，并设置端子D1-D8的数据。由于信号X2是通过连接OR电路G6，G7，G8和NOR电路G9得到的，如本发明的图所示，信号X2在信号Y2的输出期间不输出，从而防止故障。

30. 发明专利

JPS5746537A Programmable counter 失效
标题翻译：可编程计数器
公开(公告)号：JPS5746537A
公开(公告)日：1982-03-17
申请号：JP12276180
申请日：1980-09-04
申请人： Nec Corp , Nippon Telegr & Teleph Corp
发明人： KATOU GIICHI , KIKUCHI HIROYUKI , IWATA ATSUSHI
IPC分类号： H03K23/66
CPC分类号： H03K23/665
摘要： PURPOSE:To shorten the time for the count execution start of a programmable counter, by providing a gate circuit having a delay circuit of four-gate components in the preceding stage of a D type FF. CONSTITUTION:When an LOAD terminal is set to L and a program data input terminal Pi is set to H, the output of an NAND gate 24 becomes H; and since an NAND gate 26 is H, a transmission gate TG28 is turned on, and a D type FF34 is set to H. Next, the LOAD terminal is set to H; and if a CEP or CET terminal is L, the output of the NAND gate 26 becomes L, and a TG31 is turned on, and the D type FF34, is held in the preceding state. When CEP and CET terminals become H together, the D type FF34 is inverted each time a clock terminal CP becomes H, and thus, count advances. Consequently, the propagation delay time to the count start is shortened to the time of four-gate components of NAND gates 25 and 26, an inverter 27, and the TG28.
摘要翻译：目的：为了缩短可编程计数器的计数执行开始的时间，通过提供具有D型FF的前级的四门分量的延迟电路的门电路。构成：当LOAD端子设置为L并且程序数据输入端子Pi设置为H时，与非门24的输出变为H; 并且由于与非门26是H，所以传输门TG28导通，D型FF34被设置为H.接下来，LOAD端被设置为H; 如果CEP或CET端子为L，则与非门26的输出变为L，TG31导通，D型FF34保持在前一状态。当CEP和CET端子变为H时，每当时钟端CP变为H时，D型FF34都反相，因此计数提前。因此，计数开始的传播延迟时间缩短为与非门25和26，逆变器27和TG28的四门组件的时间。

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