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21. 发明专利

JP2006049728A Semiconductor memory and its manufacturing method 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2006049728A
公开(公告)日：2006-02-16
申请号：JP2004231578
申请日：2004-08-06
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L21/768 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/0491 , H01L21/7682 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To avoid the generation of a void in a formation prospective region of linearly arranged bit line contacts CB. SOLUTION: A semiconductor memory is loaded on a semiconductor chip 100; and has bit lines BL, source lines SL, and word lines WL that are perpendicular to the bit lines BL. The memory comprises: bit line side selector gate lines SGD and source line side selector gate lines SGS which are adjacent to both ends of the word line WL arranged in the bit line BL direction, and are arranged in parallel with the word line WL; a memory cell transistor MT arranged at the intersection of the bit line BL and the word line WL, and a selector gate transistor ST arranged at the intersection of the bit line BL and the selector gate line SGD; the bit line contacts CB arranged in the word line direction between the bit line side selector gate lines SGD; and a source line contact CS arranged in the word line direction between the source line side selector gates SGS, wherein an interval L1 between the bit line side selector gate lines SGD is larger than an interval L2 between the source line side selector gate lines SGS. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了避免在线性排列的位线触点CB的形成前景区域中产生空隙。解决方案：半导体存储器装载在半导体芯片100上; 并且具有垂直于位线BL的位线BL，源极线SL和字线WL。该存储器包括：与位线BL方向排列的字线WL的两端相邻的位线侧选择栅极线SGD和源极侧选择栅极线SGS，与字线WL并联布置; 布置在位线BL和字线WL的交点处的存储单元晶体管MT以及布置在位线BL和选择栅极线SGD的交点处的选择栅晶体管ST; 布置在位线侧选择栅极线SGD之间的字线方向上的位线接点CB; 以及在源极侧选择栅SGS之间的字线方向上布置的源极线接触CS，其中位线侧选择栅极线SGD之间的间隔L1大于源极侧选择栅极线SGS之间的间隔L2。版权所有（C）2006，JPO＆NCIPI

22. 发明专利

JP2005268619A Nonvolatile semiconductor memory device and its manufacturing method 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2005268619A
公开(公告)日：2005-09-29
申请号：JP2004080809
申请日：2004-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , MATSUNAGA YASUHIKO , SAKUMA MAKOTO
IPC分类号： H01L21/76 , G11C16/04 , H01L21/28 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/94
CPC分类号： G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with an improved operational reliability, and also to provide a method for manufacturing the nonvolatile semiconductor device. SOLUTION: This nonvolatile semiconductor memory is provided with a first MOS transistor and a second MOS transistor. The first MOS transistor is formed on a first device area enclosed by a first device separation area via a first gate insulting film and has a gate width direction edge on the above first device separation area. The second MOS transistor is provided with the second gate electrode which is formed on a secondary device area enclosed by a secondary device separation area via a second gate insulating film whose thickness is double the film thickness of the above first gate insulating film and has a gate width direction edge on the above second device separation area. In addition, the width from the contact position of the above first device separation area and the above first gate insulating film to the edge of the top of the above first element separation area is equal to that from the contact position of the above second device separation area and the above second gate insulating film to the edge of the top of the above second device separation area. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有改进的操作可靠性的非易失性半导体存储器件，并且还提供一种用于制造非易失性半导体器件的方法。解决方案：该非易失性半导体存储器设置有第一MOS晶体管和第二MOS晶体管。第一MOS晶体管形成在由第一器件分离区域经由第一栅极绝缘膜包围的第一器件区域上，并且在上述第一器件分离区域上具有栅极宽度方向边缘。第二MOS晶体管设置有第二栅电极，该第二栅电极形成在由次级器件分离区域包围的次级器件区域上，第二栅极绝缘膜的厚度是上述第一栅极绝缘膜的膜厚度的两倍，并具有栅极宽度方向边缘在上述第二设备分离区域上。此外，从上述第一器件分离区域和上述第一栅极绝缘膜的接触位置到上述第一元件分离区域的顶部的边缘的宽度等于从上述第二器件分离的接触位置的宽度区域和上述第二栅极绝缘膜到上述第二器件分离区域的顶部的边缘。版权所有（C）2005，JPO＆NCIPI

23. 发明专利

JP2005071558A Nonvolatile semiconductor storage device and method of operating the same, manufacturing method, semiconductor integrated circuit, and system 有权
标题翻译：非易失性半导体存储器件及其操作方法，制造方法，半导体集成电路和系统
公开(公告)号：JP2005071558A
公开(公告)日：2005-03-17
申请号：JP2003330399
申请日：2003-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： ICHIGE MASAYUKI , ARAI FUMITAKA , SUGIMAE KIKUKO
IPC分类号： G11C16/06 , G11C11/00 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , H01L21/8246 , H01L21/8247 , H01L27/00 , H01L27/10 , H01L27/115 , H01L29/74 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/005 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device having high-density/high-speed rewritable memory cells and having a high degree of flexibility in which a writing/erasure unit is small or can be optionally set. SOLUTION: There are provided: a plurality of word lines WL arranged in a row direction; bit lines DQ arranged in a column direction orthogonal to the word lines; memory cell transistors arranged in the column direction each having a charge storage layer in which a charge storage state is controlled by one of the plurality of word lines; and memory cell transistor trains MSGm and MSGn functioning as selection gates, in each of which the transistor in an enhancement mode is formed by injecting charge into the charge storage layer in the memory transistor. One or both of the first selection transistor and the second section transistor for selecting the arranged memory cell transistor may be formed of the memory cell transistors functioning as the selection gates. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高密度/高速可重写存储单元的非易失性半导体存储装置，并且具有写入/擦除单元较小或可选择地设置的高度灵活性。解决方案：提供：沿行方向布置的多个字线WL; 布置在与字线正交的列方向上的位线DQ; 沿列方向配置的存储单元晶体管，每个具有电荷存储层，其中电荷存储状态由多个字线之一控制; 存储单元晶体管串MSGm和MSGn用作选择栅极，其中通过向存储晶体管中的电荷存储层注入电荷而形成增强模式的晶体管。用于选择布置的存储单元晶体管的第一选择晶体管和第二部分晶体管中的一个或两个可以由用作选择栅极的存储单元晶体管形成。版权所有（C）2005，JPO＆NCIPI

24. 发明专利

JP2005026589A Semiconductor memory and its manufacturing method 审中-公开
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2005026589A
公开(公告)日：2005-01-27
申请号：JP2003192491
申请日：2003-07-04
申请人： Toshiba Corp , 株式会社東芝
发明人： SATOU ATSUYOSHI , SAKUMA MAKOTO , ARAI FUMITAKA
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory and its manufacturing method, in which a gate insulating film of a peripheral circuit part can be formed thinner than the gate insulating film of a cell part, and a selective transistor in a memory cell column can be made fine.
SOLUTION: A memory cell transistor comprises a gate electrode structure composed of a gate insulating film 2 of the cell part, a first conductive layer 3, a conductive interlayer insulating film 4, and a second conductive layer 7 insulated from the first conductive layer 3 by the conductive interlayer insulating film 4. The selective transistor comprises a gate electrode structure composed of the gate insulating film 2 of the cell part, the first conductive layer 3, the conductive interlayer insulating film 4, and the second conductive layer 7 which is electrically connected to the first conductive layer 3 at an opening of the conductive interlayer insulating film 4. Peripheral circuits (21, 22, 23, 24) have a peripheral circuit transistor which comprises the gate electrode structure composed of a gate insulating film 10 of the peripheral circuit part thinner than the gate insulating film 2 of the cell part.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体存储器及其制造方法，其中外围电路部分的栅极绝缘膜可以形成为比单元部分的栅极绝缘膜更薄，并且存储器中的选择性晶体管细胞柱可以做好。解决方案：存储单元晶体管包括由电池部分的栅极绝缘膜2，第一导电层3，导电层间绝缘膜4和与第一导电层绝缘的第二导电层7组成的栅电极结构层3由导电层间绝缘膜4构成。选择晶体管包括由电池部分的栅极绝缘膜2，第一导电层3，导电层间绝缘膜4和第二导电层7构成的栅电极结构，在导电层间绝缘膜4的开口处电连接到第一导电层3.外围电路（21,22,23,24）具有外围电路晶体管，其包括由栅极绝缘膜10构成的栅电极结构外围电路部分比电池部分的栅极绝缘膜2薄。版权所有（C）2005，JPO＆NCIPI

25. 发明专利

JP2004356580A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2004356580A
公开(公告)日：2004-12-16
申请号：JP2003155474
申请日：2003-05-30
申请人： Toshiba Corp , 株式会社東芝
发明人： NAGASAKA SHIGERU , ARAI FUMITAKA , UMEZAWA AKIRA
IPC分类号： G11C16/06 , G11C11/00 , G11C16/04 , G11C16/30 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/30 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which simplifies its manufacturing process. SOLUTION: The nonvolatile semiconductor memory device is provided with a memory cell MC, which includes a charge storage layer 31 and a first MOS transistor MT which is furnished with a control gate 32 formed on the charge storage layer 31 via an intergate insulating film 32, and boosting circuits 17, 18 for generating the voltages to be supplied to the memory cell MC, wherein the boosting circuits 17, 18 are formed on a semiconductor substrate 100. The nonvolatile semiconductor memory device is also provided with a capacitor element 52, which includes a capacitor insulating film 62 formed on mutually separated first and second semiconductor layers 60, 61, on the upper faces and the side faces of the first and second semiconductor layers 60, 61, and on the semiconductor substrate 100 between the first and second semiconductor layers 60, 61, with the same material as that of the intergate insulating film 32, and a third semiconductor layer 63 formed on the capacitor insulating film 62, electrically connected to the first semiconductor layer 60, and electrically isolated from the second semiconductor layer 61. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种简化其制造工艺的非易失性半导体存储器件。解决方案：非易失性半导体存储器件设置有存储单元MC，存储单元MC包括电荷存储层31和第一MOS晶体管MT，第一MOS晶体管MT配备有通过隔间绝缘体形成在电荷存储层31上的控制栅极32 薄膜32和用于产生要提供给存储单元MC的电压的升压电路17,18，其中升压电路17,18形成在半导体衬底100上。非易失性半导体存储器件还设置有电容器元件52 其包括在第一和第二半导体层60,61的上表面和侧面上的相互分离的第一和第二半导体层60,61上形成的电容器绝缘膜62，以及在第一和第二半导体层具有与栅极间绝缘膜32相同的材料的第二半导体层60,61以及形成在电容器绝缘膜6上的第三半导体层63 2，电连接到第一半导体层60，并与第二半导体层61电隔离。版权所有：（C）2005，JPO＆NCIPI

26. 发明专利

JP2004185690A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2004185690A
公开(公告)日：2004-07-02
申请号：JP2002349199
申请日：2002-11-29
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUNAGA YASUHIKO , YAEGASHI TOSHITAKE , ARAI FUMITAKA
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/10
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing Vpass stress irrespective of the method for controlling the channel voltage when sequential writing is carried out. SOLUTION: The nonvolatile semiconductor storage device is provided with a NAND type memory cell array 11, a pressure boosting circuit 15, a row decoder 13, a bit line control circuit 12, and a column decoder 14. When sequential writing is carried out, the size of an intermediate voltage is changed according to the position of a selected gate line from the pressure boosting circuit 15 through the row decoder 13, or a plurality of intermediate voltages are used when the en-block writing of the selected control gate line is carried out. When the sequential writing is employed, focusing on the fact that the size of all erroneous writing stress depends on the position of a writing word line, a writing system is changed according to the position of the writing word line to reduce all the erroneous writing stress. Thus, erroneous writing is surely prevented. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够降低Vpass应力的非易失性半导体存储器件，而与执行顺序写入时控制沟道电压的方法无关。解决方案：非易失性半导体存储装置设置有NAND型存储单元阵列11，升压电路15，行解码器13，位线控制电路12和列解码器14.当进行顺序写入时根据所选择的栅极线从升压电路15通过行解码器13的位置改变中间电压的大小，或者当所选择的控制栅极的写入时，使用多个中间电压线路进行。当采用顺序写入时，注重所有错误写入应力的大小取决于写入字线的位置的事实，写入系统根据写入字线的位置而改变，以减少所有错误的写入应力。因此，可以防止错误的写入。版权所有（C）2004，JPO＆NCIPI

27. 发明专利

JP2012178473A Nonvolatile semiconductor storage device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2012178473A
公开(公告)日：2012-09-13
申请号：JP2011040918
申请日：2011-02-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA , NAGASHIMA MASASHI , MEGURO TOSHITAKA , TAKEKIDA HIDEHITO , YAMADA KENTA
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , G11C16/0466 , H01L27/11551 , H01L29/66825 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of being laminated at a low bit cost.SOLUTION: In the nonvolatile semiconductor storage device which includes a first memory cell array layer 10, a first insulating layer 31 and a second memory cell array layer 20, the first memory cell array layer 10 has a first NAND cell unit NU1 provided with a plurality of first memory cells MC1, the first memory cell MC1 has a first semiconductor layer 11, a first gate insulating film 12 formed thereon and a first floating gate 13, the second memory cell array layer 20 has a second NAND cell unit NU2 provided with a plurality of second memory cells MC2, the second memory cell MC2 has a second floating gate 23, a second gate insulating film 22 and a second semiconductor layer 21, and a control gate 33 extending in a second direction orthogonal to a first direction is formed on both side faces in the first direction of the vertically continuous first and second floating gates 13 and 23.
摘要翻译：要解决的问题：提供能够以低位成本层压的非易失性半导体存储装置。解决方案：在包括第一存储单元阵列层10，第一绝缘层31和第二存储单元阵列层20的非易失性半导体存储器件中，第一存储单元阵列层10具有提供的第一NAND单元单元NU1 与多个第一存储单元MC1相同，第一存储单元MC1具有第一半导体层11，形成在其上的第一栅极绝缘膜12和第一浮置栅极13，第二存储单元阵列层20具有第二NAND单元单元NU2 设置有多个第二存储单元MC2，第二存储单元MC2具有第二浮置栅极23，第二栅极绝缘膜22和第二半导体层21，以及控制栅极33，其在与第一方向正交的第二方向上延伸形成在垂直连续的第一和第二浮动门13和23的第一方向的两个侧面上。版权所有（C）2012，JPO＆INPIT

28. 发明专利

JP2012069193A Nonvolatile semiconductor memory device and its control method 审中-公开
标题翻译：非线性半导体存储器件及其控制方法
公开(公告)号：JP2012069193A
公开(公告)日：2012-04-05
申请号：JP2010212221
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： SAKAMOTO WATARU , ARAI FUMITAKA
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/10 , G11C16/3418 , H01L21/28273 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of being operated at a high speed with high reliability and its control method.SOLUTION: The nonvolatile semiconductor memory device includes a cell group with a first memory cell and a second memory cell arranged adjacent to a first direction to the first memory cell, and a writing circuit. One of the first and second memory cells is used for storing data and the other is used for adjusting a threshold of the partner. When the writing circuit writes data in the first memory cell of the cell group, a voltage is applied to the second memory cell of the cell group, so that a threshold voltage of the first memory cell of the cell group is adjusted to be higher than a desired first threshold voltage.
摘要翻译：要解决的问题：提供一种能够高可靠性地运行的非易失性半导体存储器件及其控制方法。解决方案：非易失性半导体存储器件包括具有第一存储单元的单元组和与第一存储单元相邻的第一方向布置的第二存储单元，以及写入电路。第一和第二存储器单元之一用于存储数据，另一个用于调整对方的阈值。当写入电路在单元组的第一存储单元中写入数据时，将电压施加到单元组的第二存储单元，使得单元组的第一存储单元的阈值电压被调整为高于期望的第一阈值电压。版权所有（C）2012，JPO＆INPIT

29. 发明专利

JP2011204856A Nonvolatile semiconductor memory device, and method of manufacturing the same 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2011204856A
公开(公告)日：2011-10-13
申请号：JP2010070009
申请日：2010-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： ARAI FUMITAKA
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582
摘要： PROBLEM TO BE SOLVED: To improve stress resistance of a memory cell array.SOLUTION: A local selection gate electrode CSG partially selects memory cell transistors MT (for example, memory cell transistors MTto MT) and then can make other memory cell transistors MT (for example, memory cell transistors MTto MT) unselected, so that a high voltage need not be applied to the memory cell transistors MT having been made unselected.
摘要翻译：要解决的问题：提高存储单元阵列的耐应力。解决方案：局部选择栅电极CSG部分地选择存储单元晶体管MT（例如，存储单元晶体管MTto MT），然后可以制造其它存储单元晶体管MT（用于例如，存储单元晶体管MTto MT）被选择，使得高电压不需要被施加到已经被选择的存储单元晶体管MT。

30. 发明专利

JP2011166162A Manufacturing method for nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器的制造方法
公开(公告)号：JP2011166162A
公开(公告)日：2011-08-25
申请号：JP2011082918
申请日：2011-04-04
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIMAE KIKUKO , ICHIGE MASAYUKI , ARAI FUMITAKA , MATSUNAGA YASUHIKO , SATO ATSUYOSHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To simultaneously achieve higher integration, higher breakdown voltage capability, higher speed, and ease in processing of a nonvolatile semiconductor memory. SOLUTION: A manufacturing method is provided for a nonvolatile semiconductor memory including: a memory cell transistor having, on a tunneling insulating film, a floating gate electrode layer, inter-gate insulating film, first and second control gate electrode layers and a metal silicide film; a high-voltage transistor having, on a high-voltage gate insulating film 21, a high-voltage gate electrode layer 51, a partially opened inter-gate insulating film 25, first and second control gate electrode layers 48, 46 and metal silicide film 53; a low-voltage transistor having, on a tunneling insulating film 20, a floating gate electrode layer 50, a partially opened inter-gate insulating film 25, first and second control gate electrode layers 48, 46 and metallic silicide film 53; and liner insulating films 27 arranged directly on source drain regions of the memory cell transistor, the high-voltage transistor and the low-voltage transistor. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：同时实现更高的集成度，更高的击穿电压能力，更高的速度和易于处理的非易失性半导体存储器。解决方案：提供一种用于非易失性半导体存储器的制造方法，包括：存储单元晶体管，其在隧道绝缘膜上具有浮栅电极层，栅极间绝缘膜，第一和第二控制栅电极层和金属硅化物膜; 在高电压栅极绝缘膜21上具有高电压栅极电极层51，部分开放的栅极间绝缘膜25，第一和第二控制栅极电极层48,46以及金属硅化物膜的高压晶体管 53; 在隧道绝缘膜20上具有浮置栅极电极层50，部分开放的栅极间绝缘膜25，第一和第二控制栅极电极层48,46和金属硅化物膜53的低电压晶体管; 以及直接布置在存储单元晶体管，高压晶体管和低压晶体管的源极漏极区上的衬垫绝缘膜27。版权所有（C）2011，JPO＆INPIT

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