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21. 发明专利

JPH02298103A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02298103A
公开(公告)日：1990-12-10
申请号：JP24574789
申请日：1989-09-20
申请人： SANYO ELECTRIC CO
发明人： YAMADA SETSU , NAGAMATSU AKIHITO , BABA SEIICHI , SAWAI TETSUO , NAKANO HARUO , NAGAMI KIMIHIKO
IPC分类号： H01L21/822 , G06F17/50 , H01L21/338 , H01L21/82 , H01L21/8252 , H01L27/04 , H01L29/778 , H01L29/812 , H01P3/08 , H01P5/08 , H01P11/00 , H03F3/60
摘要： PURPOSE:To improve the manufacture yield by forming an active element on a substrate, measuring the characteristic of the formed active element, simulating the circuit pattern of a passive circuit element based on the measuring result and plotting the circuit pattern obtained through the simulation. CONSTITUTION:A high electron mobility transistor(HEMT) is formed on a GaAs substrate 1 and the static characteristic and the high frequency characteristic of the formed HEMT are measured by using a wafer prober. Based on the measured characteristic result, the size of the electrode pattern of the passive circuit element is calculated by simulation. The result of the calculation is inputted to a CAD of an electron beam exposure device or a converged ion beam exposure device. The device is used to plot the pattern with the direct exposure light onto the resist on the substrate 1 through the radiation of the electron beam or the converged ion beam. As a result, the dispersion in the characteristic of the active element is cancelled and the semiconductor circuit with excellent matching of both elements is manufactured.

22. 发明专利

JPH01212370A METHOD FOR MEASURING CHARACTERISTICS OF MICROWAVE SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH01212370A
公开(公告)日：1989-08-25
申请号：JP8681888
申请日：1988-04-07
申请人： SANYO ELECTRIC CO
发明人： NISHIDA MASAO , SAWAI TETSUO , HARADA YASOO
IPC分类号： G01R31/26 , H01L21/66
摘要： PURPOSE:To easily perform measurement by eliminating the necessity for detaching the connection part of a microwave semiconductor element and an input side tuner, by setting at least four points as the input signal source reflection coefficient of the microwave semiconductor element being an object to be measured and measuring a noise index or gain with respect to said set values. CONSTITUTION:The microwave noise due to a noise source 1 is inputted to a microwave semiconductor element 5 to measure the noise parameter and/or gain parameter of said element 5. At least four points are set as the input signal source reflection coefficient of the element 5 by adjusting the input side tuner 4 provided between the noise source 1 and the element 5. Then, a noise index or gain for maximizing the gain of the element 5 is measured with respect to each set value of said reflection coefficient. Further, from each measured value of said reflection coefficient and the noise index or gain, the noise parameter and/or gain parameter of the element is led out.

23. 发明专利

JP2007294863A Circuit apparatus 审中-公开
标题翻译：电路设备
公开(公告)号：JP2007294863A
公开(公告)日：2007-11-08
申请号：JP2007021274
申请日：2007-01-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKANO SHINYA , TAKANO HIROSHI , SAWAI TETSUO , USUI RYOSUKE
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L23/142 , H01L23/3737 , H01L23/467 , H01L23/498 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L2224/45124 , H01L2224/45144 , H01L2224/48139 , H01L2224/48227 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/0203 , H05K1/0265 , H05K3/06 , H05K3/202 , H05K3/4602 , H05K2201/0352 , H05K2201/10969 , H05K2203/0369 , H05K2203/049 , H05K2203/1476 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a circuit apparatus having excellent heat dissipation properties and capable of suppressing the lowering of reliability of the circuit apparatus by heat generated from a circuit element. SOLUTION: This circuit apparatus comprises: a metal substrate 20; and a plurality of circuit elements 10a, 10b loaded on the metal substrate 20, and electrically connected with the metal substrate 20. The metal substrate 20 comprises a copper plate excellent in thermal conductivity, and is divided into a plurality of regions (such as copper plates 1a, 1b which are loading regions of the circuit elements 10a, 10b, and copper plates 1c, 1d, 1e which are a connecting region of bonding wires 11a, 11b) by insulating films 4 in which a filler for enhancing a thermal conductivity is incorporated in a resin. Further, the circuit elements 10a, 10b have each independent acting potential on the surface of the circuit element turning to the metal substrate, and each of them is provided on each different copper plate 1a, 1b. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有优异的散热性能并且能够通过由电路元件产生的热量来抑制电路装置的可靠性降低的电路装置。解决方案：该电路装置包括：金属基板20; 以及负载在金属基板20上并与金属基板20电连接的多个电路元件10a，10b。金属基板20包括导热性优异的铜板，并分为多个区域（例如铜作为用于提高导热性的填充物的绝缘膜4是作为接合线11a，11b的连接区域的电路元件10a，10b和铜板1c，1d，1e的负载区域的板1a，1b 并入树脂中。此外，电路元件10a，10b在电路元件的表面上具有转向金属基板的每个独立的作用电位，并且它们中的每一个设置在每个不同的铜板1a，1b上。版权所有（C）2008，JPO＆INPIT

24. 发明专利

JP2007096035A Circuit and circuit mounting body 审中-公开
标题翻译：电路和电路安装体
公开(公告)号：JP2007096035A
公开(公告)日：2007-04-12
申请号：JP2005284133
申请日：2005-09-29
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NAKANO SHINYA , IMAOKA SHUNICHI , TAKANO HIROSHI , SAWAI TETSUO
IPC分类号： H01L23/34 , H01L23/28
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress the temperature rise of air between a circuit and a mounting board which mounts the circuit by BGA etc. SOLUTION: The circuit 10 has a circuit board 20, circuit elements 30 mounted on the circuit board 20, and a seal resin 40 sealing the circuit elements 30. The circuit 10 comprises through-holes 50 piercing the seal resin 40 and the circuit board 20. When the circuit 10 is mounted on a mounting board 60, air between the circuit 10 and the mounting board 60 is exhausted above the seal resin 40 through the through-holes 50 as the temperature rises. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过BGA等来抑制电路和安装电路之间的空气温度升高。解决方案：电路10具有电路板20，电路元件30安装在电路板20以及密封电路元件30的密封树脂40.电路10包括刺穿密封树脂40和电路板20的通孔50.当电路10安装在安装板60上时，电路之间的空气 10，并且随着温度升高，安装板60通过通孔50在密封树脂40上方排出。版权所有（C）2007，JPO＆INPIT

25. 发明专利

JP2006303464A Wiring board and circuit device 有权
标题翻译：接线板和电路设备
公开(公告)号：JP2006303464A
公开(公告)日：2006-11-02
申请号：JP2006075339
申请日：2006-03-17
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： SAIDA ATSUSHI , IMAOKA SHUNICHI , SAWAI TETSUO
IPC分类号： H01L23/12
CPC分类号： H05K1/024 , B32B15/08 , H05K1/0242 , H05K1/0298 , H05K3/4688 , H05K2201/0191 , H05K2201/035 , H05K2201/0715 , H05K2201/098 , Y10T428/24917 , Y10T428/24926
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein thinning and/or reduction of transmission loss is achieved. SOLUTION: The wiring board 10 comprises a first conductor 20 and a second conductor 30 whose electrical potentials are equal to each other, a dielectric layer 40 provided between the first conductor 20 and the second conductor 30, and a third conductor 50 embedded in the dielectric layer 40. In the wiring board 10, the film thickness ha of the first region 42 of the dielectric layer 40 positioned between the third conductor 50 and the first conductor 20 is thicker than the film thickness hb of the second region 44 of the dielectric layer 40 positioned between the third conductor 50 and the second conductor 30. Further, the cross sectional form of the third conductor 50 is a trapezoidal shape, and angles θ1 and θ2 are obtuse angles at both ends of the third conductor 50 on the second conductor 30 side. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供实现传输损耗减薄和/或减少的布线板。解决方案：布线板10包括第一导体20和电位彼此相等的第二导体30，设置在第一导体20和第二导体30之间的电介质层40和嵌入的第三导体50 在布线板10中，位于第三导体50和第一导体20之间的电介质层40的第一区域42的膜厚度ha比第二导电体50的第二区域44的膜厚度hb厚位于第三导体50和第二导体30之间的电介质层40.此外，第三导体50的截面形状为梯形，角度θ1和θ2在第三导体50的两端的钝角第二导体30侧。版权所有（C）2007，JPO＆INPIT

26. 发明专利

JP2000223902A SWITCH CIRCUIT DEVICE 失效
公开(公告)号：JP2000223902A
公开(公告)日：2000-08-11
申请号：JP2665099
申请日：1999-02-03
申请人： SANYO ELECTRIC CO
发明人： YAMAGUCHI TSUTOMU , SAWAI TETSUO
IPC分类号： H01P1/15 , H03K17/693 , H04B1/18 , H04B1/44
摘要： PROBLEM TO BE SOLVED: To provide a switch circuit device which can improve electric breakdown power and high output through low-voltage operation. SOLUTION: An FET 10 is connected between a node Pta connected to a terminal ANT and a Ptx connected to a terminal TX and an FET 20 is connected to a node Pra connected to the terminal ANT and a node Prx connected to a terminal RX. An additional capacitor 70 is connected between the gate Prg of the FET 10 and the node Pta. And an additional capacitor 80 is connected between a gate Prg of the FET 20 and the node Pra. Mutually complementary control signals Vc1 and Vc2 are applied to the gates of the FETs 10 and 20. The node Ptx is connected to a bias terminal BT through a large resistor 50 and the node Prx is connected to a bias terminal BR through a large resistor 60. The bias terminals BT and BR are supplied with a high level voltage Vhigh.

27. 发明专利

JPH1155013A INTEGRATED CIRCUIT, RESONANCE CIRCUIT, BIAS CIRCUIT, FEEDBACK CIRCUIT, HIGH FREQUENCY PROCESSING CIRCUIT, MATCHING CIRCUIT AND STUB 失效
公开(公告)号：JPH1155013A
公开(公告)日：1999-02-26
申请号：JP15036098
申请日：1998-05-29
申请人： SANYO ELECTRIC CO
发明人： NISHIDA MASAO , SAWAI TETSUO
IPC分类号： H01G4/40 , H01P1/00 , H01P7/00 , H03F3/60 , H03H5/02
摘要： PROBLEM TO BE SOLVED: To enable miniaturization, to provide satisfactory characteristics and further to enable production through a simple process with a few elements. SOLUTION: A chip capacitor 4 is arranged on a microstrip conductor 3 consisting of a microstrip line. The chip capacitor 4 has a dielectric 5 and electrodes 6 and 7 provided at both terminals. The electrodes 6 and 7 of the chip capacitor 4 are connected to the microstrip conductor 3. A resonance frequency is determined from a length L of the microstrip conductor 3 between the electrodes 6 and 7 of the chip capacitor 4, the dielectric constant and thickness of a dielectric substrate 1, and the capacitance value of the chip capacitor 4.

28. 发明专利

JPH09293828A MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JPH09293828A
公开(公告)日：1997-11-11
申请号：JP10823996
申请日：1996-04-26
申请人： SANYO ELECTRIC CO
发明人： HIRAI TOSHIKAZU , UDA NAONORI , NISHIDA MASAO , SAWAI TETSUO , HONDA KEIICHI , HARADA YASOO
IPC分类号： H01L25/18 , H01L23/50 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To provide a multi-chip package and manufacturing method thereof which realizes a small sized structure and improves the reliability. SOLUTION: An inner lead 1 made of a conductor such as Cu alloy or Fe alloy type e.g. phosphor bronze has dies for mounting chips 2a, 2b, many lead pins 1b and bridges. The chips 2a, 2b are adhered to each die with a conductive resin adhesive and electrodes on the chips 2a, 2b and corresponding lead pins 1b are connected through binding wires 3 made of Au. The lead 1 with the chips mounted thereon is bent so as to position the chips one above the other. The chips 2a, 2b are molded with a molding resin 4, and the lead pins 1b extending outside this resin are bent and cut to obtain a desired package.

29. 发明专利

JPH09186550A CHIP MOUNT BASE, PACKAGE USING IT AND SURFACE ACOUSTIC WAVE FILTER 失效
公开(公告)号：JPH09186550A
公开(公告)日：1997-07-15
申请号：JP34168695
申请日：1995-12-27
申请人： SANYO ELECTRIC CO
发明人： UDA NAONORI , KOBAYASHI TAIZO , SAWAI TETSUO , HARADA YASOO
IPC分类号： H01L41/09 , H03H9/25
摘要： PROBLEM TO BE SOLVED: To provide a package in which an electric short-circuit is interrupted and noise invasion is prevented by providing individual grounding electrodes apart from each other to the mount base. SOLUTION: A mount substrate 1 is made of an insulation material and usually a package 2 of a SAW filter, various circuits and an IC or the like are mounted, and a common ground electrode 1a is provided to a lower side. The package 2 is made up of a package lower body 11 whose middle part is recessed as a hollow rectangular parallelepiped making of an insulation material such as ceramic, plastic, alumina or BT resin, and of a cover 19. Die pads 12b, 12c apart horizontally independently with a middle surface of a bottom wall 12 as a border are formed to a package lower part 11 by means of metallic plating. Furthermore, the chip 3 of the SAW filter is placed so as to be bridged over both the die pads 12b, 12c.

30. 发明专利

JPH08139014A SWITCHING CIRCUIT DEVICE 失效
公开(公告)号：JPH08139014A
公开(公告)日：1996-05-31
申请号：JP27615294
申请日：1994-11-10
申请人： SANYO ELECTRIC CO
发明人： UDA NAONORI , SAWAI TETSUO , NISHIDA MASAO , HIRAI TOSHIKAZU , HARADA YASOO
IPC分类号： H01L27/06 , H01L21/06 , H01L21/8232 , H03K17/687 , H03K17/693
摘要： PURPOSE: To provide a switching circuit device wherein insertion loss is reduced without enlarging the circuit area. CONSTITUTION: In a switching circuit device formed constituted of FET's 1-10 on a GaAs substrate 100, the GaAs substrate 100 is made thicker than or equal to 300μm, preferably thicker than or equal to 400μm, e.g. 450μm. Thereby, insertion loss is reduced, and linearity of input and output power characteristics and distortion characteristics are improved.

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