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21. 发明专利

JPH06303268A PHASE COMPARATING CIRCUIT AND DEMODULATING CIRCUIT PROVIDING THE SAME 失效
公开(公告)号：JPH06303268A
公开(公告)日：1994-10-28
申请号：JP31060693
申请日：1993-12-10
申请人： HITACHI LTD
发明人： MATSUBARA OSAMU , YOKOTA MITSUKUNI , IGARASHI YUUKI , ISHIHARA HAYATO , YAMAKIDO KAZUO , OKAZAKI TAKAO , FURUKAWA KATSUHIRO , AKIYAMA HIROKI
IPC分类号： H03D3/00 , H03D3/14 , H04L27/22 , H04L27/227
摘要： PURPOSE:To execute phase comparison with high precision in a phase comparing circuit. CONSTITUTION:The circuit is the phase comparing circuit for detecting phase difference between an input signal VIN and a referring signal LO to be reference. It is provided with a phase difference detecting means 20 outputting a pulse with pulse width corresponding to phase difference between the input signal VIN and the referring signal LO, a voltage converting means 11 converting the pulse outputted from the phase difference detecting means 20 into a voltage value corresponding to the pulse width of the pulse, an analog/ digital converting means 13 converting the voltage value outputted from the voltage converting means 11 into a digital value based on the voltage value to be reference, an adjusting means 12 adjusting the voltage value to be reference in the analog/digital converting means 13 and a control means 41 controlling the adjusting means to execute adjustment and outputting an adjusting signal for adjustment.

22. 发明专利

JPH06152671A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06152671A
公开(公告)日：1994-05-31
申请号：JP31642692
申请日：1992-10-30
申请人： HITACHI LTD , KOKUSAI ELECTRIC CO LTD
发明人： KITA MASAHITO , OKAZAKI TAKAO , YAMAKIDO KAZUO , URABE KENZO
IPC分类号： H03D3/00 , H03D3/02 , H04L27/22 , H04L27/233
摘要： PURPOSE:To obtain a DC voltage signal corresponding to a phase difference with high accuracy by using a phase control circuit so as to generate a signal with a pulse width corresponding to the phase difference of two input pulses and applying the signal to an LPF through a CMOS inverter. CONSTITUTION:A pulse signal having a pulse width of an input pulse from terminals 1, 2 and having a phase proportional to a phase difference is outputted from an output of an exclusive OR circuit 11. The pulse signal is waveform- shaped by a waveform shaping circuit 50 and converted into a stable pulse signal independently of fluctuation of a power supply voltage by a switch circuit 51 utilizing the CMOS inverter circuit. Then a dummy MOS circuit 53 cancels a feed-through noise generated from the circuit 51. An output of the circuit 53 is smoothed by an active LPF circuit 54. The smoothed DC voltage is outputted from a terminal 3 through an output buffer 56 comprising a voltage follower circuit.

23. 发明专利

JPH05175803A VOLTAGE COMPARING CIRCUIT AND ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPH05175803A
公开(公告)日：1993-07-13
申请号：JP35702491
申请日：1991-12-25
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KUDO MASAKI , TANBA HIROKO , YAMAKIDO KAZUO
IPC分类号： H03F3/45 , H03K5/08 , H03M1/12
摘要： PURPOSE:To provide a voltage comparing circuit capable of high-speed and high-precision voltage comparing operation with a low voltage and small power consumption. CONSTITUTION:A differential amplifying circuit 4 which differentially amplifies input voltages to output complementary signals to output terminals and has a first switch circuit which can selectively short-circuit the output terminals, clocked inverters 5 and 6 which have input terminals coupled to respective output terminals of the differential amplifying circuit 4, a second switch circuit M8 which selectively short-circuits the outputs of clocked inverters 5 and 6, and latch circuits 9 and 10 which hold complementary signals outputted from clocked inverters 5 and 6 are included to constitute a voltage comparing circuit 1. Clocked inverters 5 and 6 are activated at a prescribed timing after turning- off of the first switch circuit to perform the data latch operation in latch circuits 9 and 10, and the second switch circuit M8 is turned off in the data latch operation period.

24. 发明专利

JPH043522A ANALOG INTEGRATED CIRCUIT 失效
公开(公告)号：JPH043522A
公开(公告)日：1992-01-08
申请号：JP10297190
申请日：1990-04-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KANAYAMA MASABUMI , YAMAKIDO KAZUO
IPC分类号： H03M1/66
摘要： PURPOSE:To improve the linearity of the output of an entire circuit by varying the number of analog switches connected to each capacitor of a weighted capacitor array or the size of the switch proportional to the capacitance. CONSTITUTION:Terminals of one side of capacitors C1-C4 of a capacitor array 1 composed of the four capacitors C1-C4 whose capacitor size is decided so that the ratio of each capacitance is 1:2:4:8 are connected in common, and the noninverting input terminal (+) of an operational amplifier 2 is connected to the common connecting point. Two analog switches S11, S12 are connected to the capacitor C1 of the capacitors C1-C4 four analog switches S21-S24 are connected to the capacitor C2, eight analog switches S31-S36 are connected to the capacitor C3 and 16 analog switches S41-S56 are connected to the capacitor C4. Thus, the quantity of feed-through generated in the analog switches is increased in proportion to the operating level. Thus, the ratio of the output level to feed-through noise is made constant and the output linearity is improved.

25. 发明专利

JPS63187842A VLSI FOR MODEM 失效
公开(公告)号：JPS63187842A
公开(公告)日：1988-08-03
申请号：JP1841487
申请日：1987-01-30
申请人： HITACHI LTD
发明人： KOJIMA YASUYUKI , YOKOSUKA YASUSHI , HAMADA NAGAHARU , ITO TSUNEO , IMAZAWA KOJI , TSUKAMOTO NOBUO , HAGIWARA YOSHIMUNE , YAMAKIDO KAZUO
IPC分类号： H04L27/18 , H04L29/10
摘要： PURPOSE:To attain one chip of a high speed MODEM by adding a PLL for timing matching among a logic circuit specific to a prescribed S/N, a conventional digital signal processor, a digital linear CODEC and a sampling timer. CONSTITUTION:The titled VLSI consists of a digital signal processor (DSP)1, a digitized linear CODEC2, a MODEM exclusive circuit (MLOGIC)3 comprising devices such as a serial interface and a sampling timer and a digital phase locked loop (DPLL)4 comprising two sets of circuits. A data from a terminal equipment is subject to modulation processing by the DSP1, inputted to the CODEC2, where the digital LPF is applied, the result is subject to D/A conversion and outputted to an I/F(interface)8. A reception signal is inputted from the I/F8 and subject to A/D conversion by the CODEC3 decoded at the DSP1 and outputted as a reception data from the I/F10 of the MLOGIC3. In such a case, the DPLL4 acts to match the sample timing designated by the MLOGIC3 with the actual timing of the CODEC2.

26. 发明专利

JPS6240887B2 失效
公开(公告)号：JPS6240887B2
公开(公告)日：1987-08-31
申请号：JP13600585
申请日：1985-06-24
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO
IPC分类号： H03M1/38 , H03M1/66 , H04B14/04

27. 发明专利

JPS6298815A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6298815A
公开(公告)日：1987-05-08
申请号：JP23735185
申请日：1985-10-25
申请人： HITACHI LTD
发明人： NODA TAKAAKI , YAMAKIDO KAZUO , KOKUBO MASARU
IPC分类号： H01L27/04 , H01L21/822 , H03F1/38 , H03H11/04
摘要： PURPOSE:To execute a level shift so that a sound signal of a comparatively low frequency has stably an optional DC level, by connecting an HPF consisting of a capacitor and a high resistance polysilicon, to an inversion input terminal and an output terminal of an operational amplifying circuit. CONSTITUTION:On the surface of an N-type semiconductor substrate 1, a P-type well area 2 is formed, and on its end part, an ohmic contact area 4 of P type is formed. Contact parts of both ends of a polysilicon layer are connected to a wiring connected to an operational amplifying circuit OP or a capacitor C2. When a bias voltage VB is supplied to a non-inversion input terminal (+) of the operational amplifying circuit OP, an analog signal Vout which is sent out of its output terminal goes to an AC signal which has set the bias voltage VB to a midpoint potential (DC level). The capacitor C2 executes an operation as an HPF due to a fact that a high resistance is provided in a parallel type.

28. 发明专利

JPS6121622A Pcm encoder 失效
标题翻译： PCM编码器
公开(公告)号：JPS6121622A
公开(公告)日：1986-01-30
申请号：JP13600585
申请日：1985-06-24
申请人： Hitachi Ltd
发明人： YAMAKIDO KAZUO
IPC分类号： H03M1/38 , H03M1/66 , H04B14/04
摘要： PURPOSE: To effer a PCM encoder having easy large circuit integration by using 8 capacitors having a capacitance ratio of binary weighting whose one end is connected in common to an input terminal to convert an analog signal into a PCM signal with fidelity to the μ the rule.
CONSTITUTION: A capacitor array circuit 2 has 8 capacitors C
0 ∼C
7 having capacitance of 2
0 , 2
1 , 2
2 ...2
7 respectively, and each end of the said capacitors is connected to an output line 200 in common connected to an inverting input of a voltage comparator 4. Signals 204, 205 are outputted at a time t
0 , and a logical circuit 22 turns on switches Y
81 and Y
91 in response thereto. Thus, a voice signal voltage (VIN) at a terminal 102 is charged in the capacitors C
0 ∼C
7 to apply switching. Then the switches Y
81 , Y
91 are turned off and a switch Y
92 is turned on at a time t
2 , and the said sampling voltage is inverted in the polarity and becomes holding.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过使用具有二进制加权电容比的8个电容器，使其一端连接到输入端，将模拟信号转换为PCM信号，使其具有保密性。构成：电容器阵列电路2具有分别具有2 <2> 2 <2>，2 <2> 2 <7>的8个电容器C0-C7，并且所述电容器的每一端连接到输出线200共同连接到电压比较器4的反相输入端。信号204,205在时刻t0输出，逻辑电路22响应于此而导通开关Y81和Y91。因此，端子102处的语音信号电压（VIN）在电容器C0-C7中被充电以进行切换。然后，开关Y81，Y91断开，开关Y92在时间t2接通，并且所述采样电压被极性反转并保持。

29. 发明专利

JPS60214654A Clock signal detecting circuit 失效
标题翻译：时钟信号检测电路
公开(公告)号：JPS60214654A
公开(公告)日：1985-10-26
申请号：JP7085884
申请日：1984-04-11
申请人： Hitachi Ltd
发明人： NISHIDA SHIGEO , YAMAKIDO KAZUO
IPC分类号： H04L7/00
CPC分类号： H04L7/0083
摘要： PURPOSE:To reduce the electrostatic breakdown strength of elements and improve the reliability of a product by connecting a parallel circuit of a capacity element and a resistance element and a switch which is turned on and off with a clock signal between a power source and the earth in series, and deciding on the output voltage of the parallel circuit and detecting the block signal. CONSTITUTION:When an external supply clock phie1 is at ''L'' of when an input terminal is open, ''L'' is supplied from NMOS4-1 to an inverter 1-1. At this time, PMOS4-2 turns off and the upper electrode V1 of a capacitor is held at ''0'' V through NMOS4-3, so that inverters 1-2 and 1-3 output ''H'' and ''L''. A clock signal phie is therefore an internally generated clock phie2. The when a clock phie1 is inputted, a potential V1 is equal to a source voltage VDD while the phie1 is at ''H''. The time constant CR depending upon the capacity value C and the on resistance R of the NMOS4-3 decreases when the clock phie1 is at ''L''. When C and R are so selected that an equation (1) where (f) is the frequency of phie1 and Vth is the threshold value of the inverter 1-2, V1>Vth, outputs of the inverters 1-2 and 1-3 are at ''L'' and ''H'', and the phie is the phie1.
摘要翻译：目的：为了降低元件的静电击穿强度，通过连接电容元件和电阻元件的并联电路以及通过电源与地之间的时钟信号接通和断开的开关来提高产品的可靠性并串联确定并联电路的输出电压并检测该块信号。构成：当外部电源时钟phie1在输入端子打开时为“L”时，“L”从NMOS4-1提供给逆变器1-1。此时，PMOS4-2截止，并且电容器的上电极V1通过NMOS4-3保持在“0”V，使得反相器1-2和1-3输出“H”和“ L“。因此，时钟信号phie是内部产生的时钟phie2。当输入时钟phie1时，电位V1等于源电压VDD，而phie1处于“H”。当时钟phie1处于“L”时，根据容量值C和NMOS4-3导通电阻R的时间常数CR减小。当选择C和R时，等式（1）其中（f）是phie1的频率，Vth是反相器1-2的阈值，V1> Vth，反相器1-2和1-3的输出是“L”和“H”，而phie是phie1。

30. 发明专利

JPS60170306A POWER SOURCE NOISE INVERTING AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS60170306A
公开(公告)日：1985-09-03
申请号：JP2503184
申请日：1984-02-15
申请人： HITACHI LTD
发明人： YAMAKIDO KAZUO , SAITOU HIROYUKI , NISHIDA SHIGEO , OZAKI NAOHIKO
IPC分类号： H03F1/30 , H03F3/16
摘要： PURPOSE:To eliminate the influence of power source noises by providing a capacitor between the source and gate of a PMOS transistor constituting an inverter together with an NMOS transistor and a parallel circuit of a capacitor and resistance between the drain and gate of the PMOS transistor. CONSTITUTION:An inverter circuit is constituted by respectively connecting the drain and gate of a PMOS transistor (TR) 6 to the drain and gate of an NMOS TR7 and sources of the TRs 6 and 7 to a power supply terminal and earthing potential. A capacitor 5 is connected between the source and gate of the TR6 and another capacitor 8 is connected between the gate and drain of the TR6. An equivalent high resistance composed of NMOS TRs 10 and 11, whose gates are connected with each other, is connected in parallel with the capacitor 8. Moreover, the TRs 10 and 11 are connected in such a way that PN junction formed between the source and well electrode and drain and well electrode have a relation of forward bias and reverse bias to each other. In such a way inverted phase voltages of power source noises are generated and influences of noises can be eliminated.

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