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21. 发明专利

JPS5852645A METHOD AND DEVICE FOR DEVELOPMENT 失效
公开(公告)号：JPS5852645A
公开(公告)日：1983-03-28
申请号：JP14947181
申请日：1981-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HIROBE YOSHIMICHI , KADOTA KAZUYA , NAKAZAWA TOMIO , NAGAO MAKI , TAGI YOUICHI
IPC分类号： G03F7/30
摘要： PURPOSE:To obtain a uniform, high-precision pattern by supplying a developer in a vapor state in the process of forming a fine pattern on a silicon substrate. CONSTITUTION:In a developing tank 11, a holding base 12 for holding a substrate 4 made of a silicon wafer upside down from above is provided. A device 14 for vaporizing a developer 15 is also provided in the developing tank 11. This developer 15 reacts chemically with exposed parts and unexposed parts of a photosensitive material on the substrate 15, and this developer 15 is vaporized by the device 14 to fill the developing tank 11. In this state, the substrate 4 held by the holding base 12 is treated by, for example, the cooling of a temperature regulator 19, and consequently the vapor of the developer 15 in the tank 11 is condensed to stick to the surface (reverse surface) of the substrate 4, covering the substrate surface uniformly. Consequently, the condensed developer 15 reacts chemically with a thin film of the photosensitive material on the substrate 4, thus developing a desired pattern.

22. 发明专利

JPS5817443A PHOTORESIST DEVELOPING METHOD AND ITS DEVICE 失效
公开(公告)号：JPS5817443A
公开(公告)日：1983-02-01
申请号：JP11503081
申请日：1981-07-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAZAWA TOMIO , KADOTA KAZUYA , HIROBE YOSHIMICHI , NAGAO MAKI , AZUMA HIDEAKI , TAGI YOUICHI
IPC分类号： H01L21/30 , G03F7/30 , H01L21/027
摘要： PURPOSE:To execute a uniform development extending over the whole surface of a wafer, by supplying a developing substance to the surface of the wafer by vapor phase, in case of development of photoresist. CONSTITUTION:In case of executing development, vapor or carrier vapor from a vapor or carrier vapor feed nozzle 7, and vapor of a developer from a developer feed nozzle 9 are fed into a developing chamber 6, respectively. Said vapor mixed with each other in the developing chamber 6, uniformly adheres onto the resist surface on a wafer 3 held on a wafer chuck 14, and development of the resist is executed. The mixing ratio of the water vapor or carrier vapor with the vapor of the developer can be adjusted so as to obtain an optimum development by adjusting flow rate adjusting valves 10 and 11. In this way, since a developing substance is fed by vapor phase, it does not occur that foreign matter adheres to the resist, or the resit peels off at the time of development, and a uniform development is obtained.

23. 发明专利

JPH02246150A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS FORMATION AND APPARATUS FOR PRODUCING IT 失效
公开(公告)号：JPH02246150A
公开(公告)日：1990-10-01
申请号：JP6584889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIGAWARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/027 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To increase a charge storage amount of a capacity element, for information storage use, of a stacked structure and to enhance an alpha-ray soft-error breakdown strength and an integration density of a DRAM by a method wherein a correction pattern which increases a surface area of a lower-layer electrode layer is formed on the lower-layer electrode structure of the capacity element, for information storage use, of the stacked structure of a memory cell of the DRAM. CONSTITUTION:A capacity element C, for information storage use, of a memory cell M is constituted in such a way that a lower-layer electrode layer 33, a dielectric film 34 and an upper-layer electrode layer 35 are laminated one after another. The capacity element C for information storage use is constituted in a so-called stacked structure. In the lower-layer electrode layer 33, a correction pattern 33A protruding in a plane direction from a region formed in a plane square shape is formed on the connection side of an n-type semiconductor region 28 and a complementary data line 50. A size of an etching mask used to process the lower-layer electrode layer 33 is reduced by reflected light; accordingly, a size of the lower-layer electrode layer 33 is made smaller than a preset value. Then, the correction pattern 33A is constituted in such a way that the size of the lower-layer electrode layer 33 is made large in anticipation of a reduced portion of the size.

24. 发明专利

JPS59134824A Method and device for manufacturing semiconductor 失效
标题翻译：用于制造半导体的方法和装置
公开(公告)号：JPS59134824A
公开(公告)日：1984-08-02
申请号：JP722883
申请日：1983-01-21
申请人： Hitachi Ltd
发明人： KADOTA KAZUYA , HIROBE YOSHIMICHI , NAGAO MAKI
IPC分类号： H01L21/027 , G03F9/00 , G05D3/00 , G05D3/12 , H01J37/32 , H01L21/30
CPC分类号： H01J37/32623
摘要： PURPOSE:To make sure of the detection of a target and thus contrive to improve the accuracy of wafer matching by removing only a target part of a resist applied on the surface of the wafer. CONSTITUTION:When the wafer 10 with the coat of a resist 11 is carried into a chamber 4, a cap 3 moves up and down and then supports the wafer on an electrode 8, thus making the inside of the chamber airtight. It is put in a required vacuum degree by introducing 5 and exhausting O2. At the same time, the position of the target 12 of the wafer 10 is confirmed, a mask 13 is moved by transferring a rod 15, thus making a window 14 coincident with the target 12, and the interval between the mask and the wafer surface is set suitably. When plasma P is generated between electrodes 7 and 8, it influences only through the window 14, and accordingly only the resist 11 at the part of the target 12 is ashed. Therefore, the irregular reflection and interference of light do not generate in the process of exposure, the target can be accurately detected, resulting in the improvement of the accuracy of matching, and then a fine circuit pattern can be formed.
摘要翻译：目的：确保目标的检测，从而通过仅去除施加在晶片表面的抗蚀剂的目标部分来提高晶片匹配的精度。构成：当具有抗蚀剂11的涂层的晶片10被携带到室4中时，盖3上下移动，然后将晶片支撑在电极8上，从而使腔室内部气密。通过引入5并排出O2，将其置于所需的真空度。同时，确认了晶片10的目标12的位置，通过转移杆15移动掩模13，从而使窗口14与目标12重合，并且掩模与晶片表面之间的间隔适当地设定。当在电极7和8之间产生等离子体P时，其仅影响窗口14，因此只有目标12的部分处的抗蚀剂11被灰化。因此，在曝光的过程中不产生光的不规则反射和干涉，可以精确地检测目标，导致匹配精度的提高，然后可以形成精细的电路图案。

25. 发明专利

JPS5584937A PHOTO MASK 失效
公开(公告)号：JPS5584937A
公开(公告)日：1980-06-26
申请号：JP15749478
申请日：1978-12-22
申请人： HITACHI LTD
发明人： KADOTA KAZUYA
IPC分类号： G03F9/00 , G03F1/00 , G03F1/48 , G03F7/20 , H01L21/027
摘要： PURPOSE:To prevent temperature rise of mask due to photo radiation and avoid drop of aligning precision, by providing a fluid jacket capable of transmitting light almost uniformly, at least on one side of a mask, and circulating a temperature- regulated fluid in this jacket. CONSTITUTION:In a photo mask used in production of integrated circuits or the like, a jacket 3 of flat light-transmitting material is provided on the back side of a mask main body 2 on which is formed a mask pattern 1, and leading pipes 4, 5 are provided in the upper and lower parts thereof. The leading pipes 4, 5 communicate with a fluid buffer 6, pump 7, flow meter 8, and valve 9, and a heat exchanger 10 and temperature regulator 11 are fitted to the buffer 6. In this setting, when light is radiated to the mask or the temperature is changed otherwise changed in the aligner, the mask may be kept at a constant temperature. If there is risk of uneven quantity of light of projection due to uneven density of the fluid in the jacket 5 or other reason, proper frequency and amplitude capable of disregarding the fluctuations are applied to the fluid by a pendulum so that occurrence of unevenness may be prevented.

26. 发明专利

JPS5374372A PLASMA CVD DEVICE 失效
公开(公告)号：JPS5374372A
公开(公告)日：1978-07-01
申请号：JP14969776
申请日：1976-12-15
申请人： HITACHI LTD
发明人： KADOTA KAZUYA
IPC分类号： C23C16/50 , C23C16/509 , H01L21/268 , H01L21/31
摘要： PURPOSE:To ensure a formation of a uniform and good-quality accumulation film by making differ partially the space between a pair of opposite electrodes.

27. 发明专利

JPH08241970A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241970A
公开(公告)日：1996-09-17
申请号：JP6474596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a disconnection defect or the like in the stepped part of the interconnection of a word line for a shunt by a method wherein a memory cell in a first region and a memory cell in a second region are connected by a common gate electrode in such a way that respective word lines are connected across both regions and a conductive layer which is the same layer as the electrode of a capacitance element is formed across both regions. CONSTITUTION: MISFET's Qs's for memory selection of a plurality of memory cells M are constituted on the main face part of p-well regions 22, and they are constituted mainly of the p-well regions 22, of gate insulating films 25, of gate electrodes 26 and of one pair of n-type semiconductor regions 28 as a source region and a drain region. The gate electrodes 26 and word lines 26 are formed respectively of the same conductive layer, and the word lines connect the respective gate electrodes 26 of the MISFET's for Qs's for memory selection of the plurality of memory cells M arranged in the row direction. In addition, n-type semiconductor regions 28 on the connection side of capacitance elements C, for information storage, of the MISFET's Qs's for memory selection are constituted integrally with n semiconductor regions 33A.

28. 发明专利

JPS61285716A RESIST COATING METHOD 失效
公开(公告)号：JPS61285716A
公开(公告)日：1986-12-16
申请号：JP12613385
申请日：1985-06-12
申请人： HITACHI LTD
发明人： ITO TETSUO , TANUMA MASAYA , NAKAGOME YOSHIYUKI , KADOTA KAZUYA , KOBAYASHI KAZUNARI
IPC分类号： B05D7/00 , B05D1/32 , B05D1/40 , B05D3/06 , G03F7/16 , H01L21/027 , H01L21/30 , H01L21/302
摘要： PURPOSE:To reduce the dispersion of development dimension, by setting the values of parameter to the values corresponding to the limiting values of fluctuation, in the case where the development dimension of the resist shows the fluctuating characteristics according to the variation of parameters in the resist coating process. CONSTITUTION:It is assumed that the allowable dispersion value of the development dimension in the photoresist process of semiconductor element is + or -DELTAlfor the designed dimension ld. If the thickness of the resist-spread film is set to be t3 by mistake, the dispersion of development dimension increases, and the number of semiconductor elements vs. the development dimension distributes as shown by the curve 11. Many elements whose film thickness exists outside the allowable range ld+ or -DELTAl are classified as unsatisfactory products. In case t1 and t2 are adopted as the set values for the thickness of the resist-coated film, the dispersion of development dimension decreases as shown by the curve 14, wherein the inferior products correspond to only the parts 15 and 16 and the inferior percentage decreases to less than 10%. Thus the dispersion of development dimension can be reduced.

29. 发明专利

JPS61213846A PATTERN FORMING METHOD 失效
公开(公告)号：JPS61213846A
公开(公告)日：1986-09-22
申请号：JP5462585
申请日：1985-03-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SUGIMOTO ARITOSHI , UEHARA ICHIRO , KADOTA KAZUYA
IPC分类号： G03C5/08 , G03F7/20 , G03F7/38 , H01L21/027
摘要： PURPOSE:To reduce the variance of photoresist dimensions to unify photoresist dimensions by performing the processing where a specific film thickness of an exposed part subjected to patterning exposure is reduced by heating or the like at least and performing exposure faintly and performing development. CONSTITUTION:Patterning exposure is performed through a mask pattern with normal dimensions to form a low exposed part 7a' in an exposed part 7a. A photoresist 7 is subjected to the processing where the film thickness of the exposed part 7a is reduced by [lambda2/(4n2)] (2N+1) (N=0, 1, 2,..., and lambda2 and n2 are the exposure light wavelength for overall faint exposure and the photoresist refractive index respectively) and the film thickness is reduced throughout by lambda2/(4n2). After this film thickness reduction processing, all of the surface of a semiconductor substrate is exposed faintly with the light having the same wavelength lambda2 as the patterning exposure light wavelength. The boundary face between the exposed part 7a and a non-exposed part 7b is linear by overall faint exposure, and the variance of dimensions of the photoresist 7 are eliminated by development.

30. 发明专利

JPS60247938A SEMICONDUCTOR MANUFACTURING DEVICE 失效
公开(公告)号：JPS60247938A
公开(公告)日：1985-12-07
申请号：JP10255784
申请日：1984-05-23
申请人： HITACHI LTD
发明人： TAKEUCHI MASARU , KADOTA KAZUYA , TANUMA MASAYA , OONARI MIKIHIKO
IPC分类号： H01L21/50
摘要： PURPOSE:To perform a highly precise control over the treatment process of a semiconductor by a method wherein, after each processing part and meaauring part constituting a manufacturing process have been arranged in series, each controlling part is connected, and the processing condition of each processing part is established based on the measured data sent from the measuring part and the value of design. CONSTITUTION:A number of treatment processes such as a gate oxidation part, an implantation part 13, a polysilicon film forming part 14, a coating part, an exposing part, a developing part and the like and the measuring processes such as an oxide film thickness measuring part 12, a photoresist film thickness measuring part 16 and the like are arranged in series horizontally, and the substrate to be processed is brought in the state wherein it can be shifted along the line of the above-mentioned arrangement. A controlling part is provided between each treatment process and measuring process. The controlling part outputs processing data based on the measured data sent from the measuring process and the designed input value and automatically controls the processing condition of each treatment process. As a result, the semiconductor manufacturing device can be formed into a line, it can be automated, the controlling accuracy can be improved, and the stabilization of the device can also be accomplished.

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