专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

JPH07226777A HIERARCHICAL NETWORK MANAGEMENT SYSTEM AND CONTROL METHOD FOR NETWORK MANAGEMENT INFORMATION 失效
公开(公告)号：JPH07226777A
公开(公告)日：1995-08-22
申请号：JP3795794
申请日：1994-02-10
申请人： HITACHI LTD
发明人： KAGEI TAKASHI , SUZUKI MICHIO , TANAKA YASUHIRO , SAITO MASATO , KUROSAKI YOSHIYUKI , FUJINO SHUJI , HASHIDA MITSUYOSHI
IPC分类号： G06F13/00 , H04L12/24 , H04L12/26 , H04L12/28 , H04L12/46 , H04L12/66
摘要： PURPOSE:To simplify the configuration of a sub-manager by allowing a communication service between a grand manager and th sub-manager to be in compliance with the IAB management standards and then to simplify the entire configuration of the management system. CONSTITUTION:A grand manager 50, a sub-manager 10 and an agent 20 manage the network in a hierarchical way. The sub-manager 10 has management information corresponding one to one to management information of the agent 20 under the control of the sub-manager 10. That is, the logical data structure (MIB) of the management information reserved by the sub-manager 10 to manage the network in hierarchical way according to the protocol SNMP is defined. The management information of the sub-manager 10 has a table structure in which information used to identify the agent is set to part of the index.

22. 发明专利

JPH07170567A PORTABLE TELEPHONE SYSTEM 失效
公开(公告)号：JPH07170567A
公开(公告)日：1995-07-04
申请号：JP15901494
申请日：1994-07-11
申请人： HITACHI LTD , KOKUSAI ELECTRIC CO LTD
发明人： FUKUSHIMA YUTAKA , TAKEMURA TETSUO , IWAKI SHINICHI , HASHIDA MITSUYOSHI , WANAMI MASAO , SHINPO ISAO , WADA MITSUHIRO , UTAKI HIROSHI , KONDOU YOSHIHIRO , YAMAMOTO YOSHINOBU , NAKAKOSHI ARATA , WATABE YUMIKO , OTA KOICHI , KUWABARA HIROSHI
IPC分类号： H04W24/04 , H04W24/06 , H04W56/00 , H04W60/04 , H04W64/00 , H04W84/04 , H04W88/08 , H04Q7/38
摘要： PURPOSE:To allow the system to provide diversified service utilizing portable telephone sets. CONSTITUTION:Data received by a portable telephone set 1 connected to a radio base station 2 connecting to an exchange 4 or the like through a radio channel are given to an error control circuit 270, in which the error of data is corrected and the corrected data are sent to a data terminal equipment 271 connected to the outside of the system via a predetermined interface. On the other hand, data sent from a data terminal equipment through a predetermined interface are sent from the portable telephone set 1 to the radio base station 2. For example, let the data terminal equipment 271 be a home security equipment, then the home security equipment is controlled from a visiting location and also makes a call to a portable telephone set carried by the user visiting to any place on a predetermined opportunity and required information or the like to the user.

23. 发明专利

JPH07170560A PORTABLE TELEPHONE SYSTEM 失效
公开(公告)号：JPH07170560A
公开(公告)日：1995-07-04
申请号：JP15901694
申请日：1994-07-11
申请人： HITACHI LTD , KOKUSAI ELECTRIC CO LTD
发明人： FUKUSHIMA YUTAKA , TAKEMURA TETSUO , IWAKI SHINICHI , HASHIDA MITSUYOSHI , WANAMI MASAO , SHINPO ISAO , WADA MITSUHIRO , UTAKI HIROSHI , KONDOU YOSHIHIRO , YAMAMOTO YOSHINOBU , NAKAKOSHI ARATA , WATABE YUMIKO , OTA KOICHI , KUWABARA HIROSHI
IPC分类号： H04W24/00 , H04W76/02 , H04W88/14 , H04Q7/22 , H04Q7/24 , H04Q7/26 , H04Q7/30 , H04Q7/34 , H04Q7/38
摘要： PURPOSE:To test a portable telephone system effciently. CONSTITUTION:Upon the receipt of a command from a test operation system Ops, a supervisory test system reserves relay using a designated channel for a test call to a radio base station BS being a test object through an ISDN exchange and gives a command of call of a test call to a test device TTR provided to a specific BS among plural base stations. The test call is connected to the supervisory test system via the BS accepting the reservation. The supervisory test system confirms the normality of the connected call.

24. 发明专利

JPH0698367A RESTRICTION SYSTEM IN MOBILE COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0698367A
公开(公告)日：1994-04-08
申请号：JP30592391
申请日：1991-11-21
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI , FUKUSHIMA YUTAKA , SHINPO ISAO
IPC分类号： H04W4/16 , H04W48/02 , H04W48/20 , H04W84/10 , H04Q7/04
摘要： PURPOSE:To provide the restriction system in the mobile body communication system in which an invalid call in a communication network is reduced and the restriction for each terminal equipment is attained. CONSTITUTION:A restriction status of a terminal equipment is recognized by using a database comprising a terminal equipment position information table representing a location of a terminal equipment 1 and a position restriction information table 20 representing the restriction state at each position to restrict a calling from the terminal equipment and an incoming call to the terminal equipment. Moreover, the registration means together with the position information of the terminal equipment 1 is stored in the table 20, and the call connection request from a terminal equipment making its position registration by an automatic position registration means is made a restriction object with priority over the call connection request from the terminal equipment making position registration by a manual position registration means.

25. 发明专利

JPS63294123A THREE-STATE CIRCUIT 失效
公开(公告)号：JPS63294123A
公开(公告)日：1988-11-30
申请号：JP12817387
申请日：1987-05-27
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI
IPC分类号： H03K19/0175 , H03K19/094
摘要： PURPOSE:To reduce the performance fluctuation of a three-state circuit, by connecting drain or source electrodes of transistors between the gates of output transistors and controlling the gate electrodes of the transistors with output controlling signals. CONSTITUTION:MOS transistors 9 and 10 which are controlled by output controlling signals are connected between the gate of a (p) channel output MOS transistor 7 and the gate of an (n) channel output MOS transistor 8. Since the MOS transistor 9 connected between the gates of the (p) and (n) channel output MOS transistors 7 and 8 is turned on when the output controlling signals are low in level, outputs of a NAND gate 5 and NOR gate 6 are set in a short-circuited state. Therefore, the data of a data input terminal are transmitted to the output MOS transistors 7 and 8 by means of an inverter circuit practically composed of a (p) channel MOS transistor 11 and (n) channel MOS transistor 19. As a result, the performance fluctuation of this three-state circuit caused by the characteristic variation of the MOS transistors can be reduced.

26. 发明专利

JPS598347A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS598347A
公开(公告)日：1984-01-17
申请号：JP11679882
申请日：1982-07-07
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： HASHIDA MITSUYOSHI , KAWARADA KUNIYASU
IPC分类号： H01L21/331 , H01L21/761 , H01L29/73
CPC分类号： H01L21/761
摘要： PURPOSE:To prevent abnormal operation between wells due to a parasitic transistor with the substrate used as the base by newly providing a well between the adjacent wells. CONSTITUTION:A semiconductor integrated circuit device employing the P-N junction separation structure uses, for example, a P type substrate 3 and provides an N well 1 and an N well 2. Another well 4 is additionally provided between the wells 1 and 2 and a potential A of the well 4 is set higher than the potential of wells 1 and 2. Thereby, the collector of a parasitic N-P-N transistor which uses the P type substrate 3 as the base is formed by the N well 4. Accordingly, even when the base and emitter junction is forward biased, a collector current can be extracted from the well 4. Therefore, any influence is applied on the well 2 and junction between the wells 1 and 2 can be prevented. This well 4 may be a well containing elements and may be provided in such a manner as surrounding the well 1.
摘要翻译：目的：通过在相邻的井之间新提供一个井，以防止基板用作基底的寄生晶体管，以防止井之间的异常操作。构成：采用PN结分离结构的半导体集成电路器件使用例如P型衬底3并提供N阱1和N阱2.另外在阱1和2之间提供另一阱4，阱4的A设定为高于阱1和2的电位。由此，使用P型衬底3作为基极的寄生NPN晶体管的集电极由N阱4形成。因此，即使当基极并且发射极结被正向偏置，可以从阱4中提取集电极电流。因此，对阱2施加任何影响，并且可以防止阱1和2之间的接合。该井4可以是容纳好的元件，并且可以以围绕井1的方式提供。

27. 发明专利

JPS5864838A SYNCHRONIZING DEVICE 失效
公开(公告)号：JPS5864838A
公开(公告)日：1983-04-18
申请号：JP16271081
申请日：1981-10-14
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI
IPC分类号： H04L7/00
摘要： PURPOSE:To synchronize devices operating in different clock rates simply, by inputting a logical product output of the 1st and the 2nd clocks to a low-frequency input terminal selecting both the clocks one of which is a multiple of the other. CONSTITUTION:In a PCM line system, an oscillator 1 oscillates a frequency, e.g., 2,048MHz and it is inputted to a counter 2, which oscillates clocks of 2,048MHz, 1,024MHz, and 8kHz frequencies and the clocks are inputted to a terminal A of a selector 3, an AND gate 7 and a decoder 4. The decoder 4 has a function setting the duty ratio, its output is inputted to a reset terminal PC of an FF5 and the 8kHz clock is inputted to a clock terminal CP of the FF5. The output of the gate 7 is inputted to a terminal B of the selector 3, and when the output of the FF5 is 1, the selector 3 selects a B input and gives an output to a terminal 6. When the output of the FF5 is zero, the selector 3 outputs an A input. The decoder 4 and the FF5 output the clocks of 1,024 and 2,048MHz to the terminal 6 in the timing ratio of 63:65.

28. 发明专利

JPS57118461A Signal detecting circuit 失效
标题翻译：信号检测电路
公开(公告)号：JPS57118461A
公开(公告)日：1982-07-23
申请号：JP305181
申请日：1981-01-14
申请人： Hitachi Ltd
发明人： HASHIDA MITSUYOSHI
IPC分类号： H04L27/26 , H04Q1/457
CPC分类号： H04Q1/4575
摘要： PURPOSE:To decrease the number of ICs which are necessary for the constitution of a signal detecting circuit for a degital signal receiver, by carrying out the operations of¦cosi¦-TH and¦cosi¦-TH+¦sini¦through an arithmetic circuit in a time sharing way. CONSTITUTION:The integral value among time windows is supplied to a shift register 1 and a D/FF2 in the form of an input signal (a). The delayed input signal (a) delivered from the register 1 and the delayed input signal (a) supplied via a code inverting circuit 3 are supplied to a selector 4. The selector 4 is controlled according to the set output state of the D/FF2, and accordingly the absolute value output (b) of the delayed input signal (a) is successively delivered from the selector 4. The¦cosi¦supplied from the selector 4 is added with a shift output (g) related to a negative certain value (-TH) which is loaded to a shift register 8 with the timing of the load signal (e) through an adder 7. Thus ¦cosi¦-TH is obtained and then supplied to the register 8 to be added with the¦sini¦given from the selector 4 through the adder 7. In such way, a prescribed result of operation is obtained.
摘要翻译：目的：为了减少构成信号信号接收机的信号检测电路所必需的IC数量，通过运算电路中的运算电路来执行“cos”-TH和“cos”-TH + 时间分享的方式。构成：时间窗口中的积分值以输入信号（a）的形式提供给移位寄存器1和D / FF2。从寄存器1发送的延迟输入信号（a）和经由码反相电路3提供的延迟输入信号（a）被提供给选择器4.选择器4根据D / FF2的设定输出状态，因此延迟输入信号（a）的绝对值输出（b）从选择器4连续发送。从选择器4提供的输入端加上与负特定值相关的移位输出（g）（-TH），其通过加法器7以负载信号（e）的定时加载到移位寄存器8.因此，获得| cosi|-TH，然后提供给寄存器8以添加... 通过加法器7从选择器4给出。以这种方式，获得规定的操作结果。

29. 发明专利

JPH03242990A PRINTED CIRCUIT BOARD 失效
公开(公告)号：JPH03242990A
公开(公告)日：1991-10-29
申请号：JP3820790
申请日：1990-02-21
申请人： HITACHI LTD
发明人： HASHIDA MITSUYOSHI
IPC分类号： H05K1/11
摘要： PURPOSE:To oscillate a plurality of timing signals by only one plug by forming the plug in a comb shape in a printed circuit board for placing electronic circuit components. CONSTITUTION:A printed circuit board 1 has a pectinated plug 4, a grounded contact 5 supplies a low level to the plug 4 in a state that the board 1 is inserted, and the plug 4 is formed to be shorter than a plug 2 for a power source. When the plug 2 is brought into contact with a contact 3, the plug 4 becomes a higher level than a pull-up resistor 6, the plug 4 is then brought into contact with the contact 5, becoming a low level, further isolated from the contact 5, becoming a high level. Thus, after the plugs 4, 5 are repeatedly connected/opened, they are finally brought into contact therewith, and a timing generator 7 connected to the plug 4 generates a plurality of timing signals with the signal as a clock signal. Thus, a plurality of timing signals can be formed from one plug.

30. 发明专利

JPH01128542A FORMING METHOD FOR WIRING PATTERN OF GATE ARRAY LSI 失效
公开(公告)号：JPH01128542A
公开(公告)日：1989-05-22
申请号：JP28536287
申请日：1987-11-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HASHIDA MITSUYOSHI , KAJIKAWA TAKANOBU
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/118
摘要： PURPOSE:To prevent a local power source potential variation position or an abnormal power source current density rising position from occurring by forming and inserting a reinforcing power source wiring pattern in response to a logic configuration, a logic block disposition. CONSTITUTION:A reinforcing power source pattern 51 is formed in response to the temporary disposition of a logic block 41 to be disposed on a basic cell row 31. Then, items of judging the necessity of the reinforcing power source and forming the reinforcing power source pattern are provided. Since allowable number or more of power gates are arranged on the row 31, a basic cell row in which a power source potential varies or a power source current density becomes allowable limit or more is employed as a vacant logic block 71, and the disposition of the logic block is corrected. Then, the pattern 51 which is passed and wired to the block 71 is formed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式