专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

JPS6299991A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6299991A
公开(公告)日：1987-05-09
申请号：JP23742885
申请日：1985-10-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IWAI HIDETOSHI , MATSUURA NOBUMI
IPC分类号： G11C11/409 , G11C11/34 , G11C11/407 , G11C11/408
摘要： PURPOSE:To obtain an input circuit, in which malfunctions to pulse-like noises are prevented, by forming an internal timing signal from the output signal of a latch circuit which is set by an operation mode signal and its delayed signal and reset by the delayed signal. CONSTITUTION:Write enable signals, the inverse of WE are fetched through a NOR gate circuit G1 and one of the output signals WE is inverted by an inverter circuit IV and delayed by a delaying circuit DEL by means of a RAS system timing signal, the inverse of R1 under a memory access state only. NOR gate circuits G2 and G3 are connected with each other under the form of a latch and an internal writing signal W1 is formed from the output terminal of the NOR gate circuit G2. Low-level ones of the write enable signals, the inverse of WE having pulse widths which are shorter than the delayed time of the delaying circuit DEL are regarded as noises and fetching of the low-level write enable signals, the inverse of WE is inhibited.

22. 发明专利

JPS6122493A Decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：JPS6122493A
公开(公告)日：1986-01-31
申请号：JP14237984
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MURANAKA MASAYA , KAJIMOTO TAKESHI , MATSUURA NOBUMI
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE: To offset leak current without increasing an occupied area, to secure a decoder output at non-selection for a long period and to prevent the multiple selection by connection a high resistance element in parallel to a precharge MOSFET and compensating the leak current.
CONSTITUTION: A node x
0 is made at H level by a precharged pulse ϕp through a P-channel FETQp. As long as any one of address input N-channel FETs Q
21 , Q
22 ... is off in the nonselective state through a row address buffer X-ADB, the node x
0 is brought into the H level nonselective state. In such a case, the leak current can be compensated by the P-channel FETQr of a high resistance element, which is always on in parallel with the FETQp, through the FETs Q
21 , Q
22 .... Thus the leak current can be canceled out without increasing an occupied area, and a decoder output at the non-selection can be secured for a long time, thereby preventing the occurrence of erroneous operation at multiple selection.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了在不增加占用面积的情况下消除泄漏电流，长时间保证解码器输出处于非选择状态，并通过连接高电阻元件并与预充电MOSFET并补偿漏电流来防止多重选择。构成：通过P沟道FETQp通过预充电脉冲激光器在H电平上使节点x0成为。只要地址输入N沟道FET Q21，Q22 ...中的任何一个在非选择状态下通过行地址缓冲器X-ADB截止，则节点x0进入H电平非选择状态。在这种情况下，可以通过FET Q21，Q22 ...总是与FETQp并联的高电阻元件的P沟道FETQr来补偿漏电流。因此，漏电流可以被取消在不增加占用面积的情况下，可以长时间确保非选择时的解码器输出，从而防止多次选择时发生错误操作。

23. 发明专利

JPS6129488A Dynamic ram 失效
标题翻译：动态RAM
公开(公告)号：JPS6129488A
公开(公告)日：1986-02-10
申请号：JP14956084
申请日：1984-07-20
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MATSUURA NOBUMI , MIYAZAWA KAZUYUKI , YANAGISAWA KAZUMASA
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE: To speed up further a high speed action and to improve an action margin by controlling the timing when the selection level of a word line is raised at a high level more than a power source voltage by means of a word line selection/activation circuit for consisting of a circuit similar to an address decoder.
CONSTITUTION: A memory cell for storing information is constituted of an information storing capacitor and an address selecting MOSFET, and selected by an address decoder R-DCR2. Synchronizing with a selecting action, an address decoder R-DCR1 constituted of circuits similar to said decoder R-DCR2 operates as an activating circuit. With the supply of an address signal, a word line selection timing signal ϕx is transmitted from a node between FETs Q39 and Q40, and its voltage is raised at a high level more than a power source V
cc of the signal ϕx by inverter circuits 1V2W1V5 serially connected to a bootstrap CB. Thus an RAM can act at a high speed, and simultaneously its action margin can be improved.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过字线选择/激活电路，当字线的选择电平升高到高于电源电压的高电平时，通过控制定时来加速进一步的高速动作并提高动作余量用于由地址解码器类似的电路组成。构成：用于存储信息的存储单元由信息存储电容器和地址选择MOSFET构成，并由地址解码器R-DCR2选择。与选择动作同步，由与解码器R-DCR2类似的电路构成的地址解码器R-DCR1作为激活电路进行动作。通过提供地址信号，从FET Q39和Q40之间的节点发送字线选择定时信号phix，并且其电压比反相器电路1V2-的信号phix的电源Vcc高出高电平， 1V5串联连接到自举CB。因此，RAM能够以高速行动，同时可以提高其动作余量。

24. 发明专利

JPS60171695A COUNTER CIRCUIT 失效
公开(公告)号：JPS60171695A
公开(公告)日：1985-09-05
申请号：JP2714684
申请日：1984-02-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MATSUMOTO TETSUO , MIYAZAWA KAZUYUKI , MATSUURA NOBUMI
IPC分类号： G11C11/406 , G11C11/34
摘要： PURPOSE:To make a counter circuit operate stably with simple constitution by compensating a decrease in a level at the time of transfer of information from a dynamic FF to a 3MOS memory circuit by a dynamic pullup circuit. CONSTITUTION:A master side of an FF is formed by cross coupling FETQ1 and Q2, precharging FETQ3 and Q4, FETQ5 and Q5' to be controlled by a timing signal, and a slave side of the FF is formed by memory capacitors C3 and C4, write FETQ9 and Q12, amplifying FETQ8 and Q11, and a 3MOS memory circuit of read FETQ7 and Q10. Moreover, an FET and a dynamic pullup circuit consisting of capacities Q13, Q14 and a C5, a Q15, a Q16 and a C6 are provided between nodal points N1 and N2 and a supply voltage VCC, and compensates a level decrease at the time of information transfer from the master to the slave side is compensated. A signal having two-fold period of that of a signal phi is securely outputted, which is supplied, and a counter circuit can stably operate.

25. 发明专利

JPS60119697A DYNAMIC RAM 失效
公开(公告)号：JPS60119697A
公开(公告)日：1985-06-27
申请号：JP22687983
申请日：1983-12-02
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： MATSUURA NOBUMI
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To improve the operating margin by operating selectively an MOSFET provided between complementary data line pairs and a power supply voltage terminal to attain active restorage operation. CONSTITUTION:Storage information of a memory cell is read to the complementary data lines DL, -DL and the level of a timing signal phi2 is decreased, then an MOSFETQ4 connected to the data line -DL brought into a low level keeps the ON state and an MOSFETQ16 is turned off. When an active restorage control signal phi reaches a high level boosted to the power voltage VCC or over, the level is given to a gate of an MOSFETQ1 through an MOSFETQ15, the Q1 is turned on so as to restore the level of the data line DL to a high level like the power voltage VCC. Since the signal phi1 is not given to the gate of an MOSFET Q3, the Q3 remains turned off. The flowing of the current from the power supply voltage terminal to the data line -DL is prevented. The leading of the low level is increased and the sensitivity is improved.

26. 发明专利

JPH06275693A DYNAMIC RAM 失效
公开(公告)号：JPH06275693A
公开(公告)日：1994-09-30
申请号：JP8557693
申请日：1993-03-20
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： MATSUURA NOBUMI , MURANAKA MASAYA , ORITO YASUNORI
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/18 , G11C29/34 , H01L21/66
摘要： PURPOSE:To provide a dynamic RAM having a testing circuit which can variously test an internal circuit. CONSTITUTION:A memory array is logically or physically divided into a plurality of blocks to be tested at a block unit. A memory array having a plurality of column address strobe signals to be accessed at a unit of a plurality of bits corresponding to the signals can test independently of the corresponding array by using the signals. Accordingly, since the test can be conducted in terms of a plurality of memory arrays which are logically or physically divided, a precise evaluation, a malfunction analysis can be executed with less samples.

27. 发明专利

JPS6180594A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6180594A
公开(公告)日：1986-04-24
申请号：JP19961684
申请日：1984-09-26
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MATSUMOTO TETSUO , MATSUURA NOBUMI
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE: To prevent an external signal from influencing the signal by the internal circuit by supplying selectively a signal formed by an internal circuit to the output side of an amplifying circuit which amplifies a signal supplied from the external terminal, executing an amplifying action selectively and changing over both signals.
CONSTITUTION: A timing signal ϕ
1 is supplied to a refreshing address buffer of a dynamic RAM, and then, an amplifying circuit, which amplifies an external address Ar, becomes an action condition. A refreshing address air and inversion ari of an internal signal from at an address counter of the internal circuit by a timing signal ϕ
2 at the time of timing without a signal ϕ
1 independently to the signal ϕ
1 , are amplified by the same amplifying circuit, become an address ai and an inversion ai and is outputted from an output end of the amplifying circuit of an address Ai. A signal by the internal circuit with an change- over output of the external address and the internal address will not be influenced by the external signal, and the refreshing, etc., of the dynamic RAM are executed properly.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了防止外部信号由内部电路影响信号，通过选择性地将内部电路形成的信号提供给放大电路的输出侧，该放大电路放大从外部端子提供的信号，选择性地执行放大动作并改变两个信号。构成：将定时信号phi1提供给动态RAM的刷新地址缓冲器，然后放大外部地址Ar的放大电路成为动作条件。通过相同的放大电路对与内部电路的地址计数器的内部信号进行更新的定时信号phi2的定时信号phi2而不具有与信号phi1独立的信号phi1的定时信号phi2，地址ai和反相ai，并从地址Ai的放大电路的输出端输出。具有外部地址和内部地址的转换输出的内部电路的信号不受外部信号的影响，动态RAM的刷新等被正确执行。

28. 发明专利

JPH0799221A BURN-IN TEST CIRCUIT FOR SEMICONDUCTOR DEVICE AND METHOD THEREFOR 失效
公开(公告)号：JPH0799221A
公开(公告)日：1995-04-11
申请号：JP9357593
申请日：1993-03-29
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： NASU TAKUMI , YAMAGUCHI YASUNORI , MATSUURA NOBUMI , IWAI HIDETOSHI , SAKUTA TOSHIYUKI
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66
摘要： PURPOSE:To apply to an insulation film field stress equivalent to or more than that by the conventional method through burn-in for a short period by accelerating the field stress between multiple-level conductive layers mutually, between a conductive layer and an accumulation electrode and between the level conductive layers for the conductive layer mutually. CONSTITUTION:The potential is fixed at 0V in the parts between a bit line 23 of a first metallic layer level and a Y line 24 of a second metallic layer level, between an accumulation electrode 22 and the line 23 of the first metallic layer level, and between an accumulation node 21 and the electrode 22. Therefore, since the stress status does not change at all, any one is selected and kinds of stress cycles are combined for a short burn-in period, so that effective field stress can be made to work to the insulation films 15, 16, 17 and 18 of respective layers.

29. 发明专利

JPH0729396A TESTING CIRCUIT FOR SEMICONDUCTOR UNIT 失效
公开(公告)号：JPH0729396A
公开(公告)日：1995-01-31
申请号：JP19682393
申请日：1993-07-14
申请人： TEXAS INSTRUMENTS JAPAN , HITACHI LTD
发明人： SUKEGAWA SHUNICHI , SHIOZAKI SHUZO , MATSUURA NOBUMI , MURANAKA MASAYA
IPC分类号： G11C29/00 , G11C29/14 , G11C29/46
摘要： PURPOSE:To provide a testing circuit for a semiconductor unit capable of registering a testing mode without registering the testing mode during normal use and applying a voltage higher than a power voltage to an outside terminal. CONSTITUTION:The coincidence of an address 1 to be inputted is detected by a decoder circuit 11 and a signal indicating the coincidence of the address 1 is latched by a latching circuit 14. The coincidence of an address 2 to be inputted when the coincident signal of the previously inputted address 1 is latched is detected by a decoder circuit 12 and a signal indicating the coincidence of the address 2 is latched by a latching signal 15. A decoder circuit 13 and a latching circuit 16 are operated by the same way as the decoder circuit 12 and the latching circuit 15 and a test enabling signal is outputted. That is, only when three addresses to be inputted continuously are in a predetermined combination, the test enabling signal is outputted and the testing mode is started.

30. 发明专利

JPS6098662A SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS6098662A
公开(公告)日：1985-06-01
申请号：JP20484983
申请日：1983-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KAJIMOTO TAKESHI , MATSUURA NOBUMI
IPC分类号： G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To reduce the noise generating in the first conductive plate by a method wherein this plate constituting the capacitance element of a dummy cell is electrically connected to the second conductive plate constituting the capacitance element of a memory cell. CONSTITUTION:The capacitance element is constructed by providing the conductive plates 17C in the memory cell array (M.ARY) and the dummy cell array (D.ARY) by extension in the row direction. These plates are provided in the column direction at fixed pitches and constitute one matrix of the DRAM. Respective plates are connected between respective array by means of a connection wire 23; thus the first conductive plate made up of a plurality of plates 17C is formed in the dummy cell array part; and the second conductive plate having a larger capacitance value than the first conductive plate is constructed in the memory cell array part. These plates are electrically connected at each end and the part other than it. Then, the second conductive plate quickly reduces the noise generating in the first conductive plate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式