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21. 发明专利

JP2003330907A Microcomputer system 审中-公开
标题翻译：微型计算机系统
公开(公告)号：JP2003330907A
公开(公告)日：2003-11-21
申请号：JP2003113567
申请日：2003-04-18
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , FUKADA KAORU , AKAO YASUSHI
IPC分类号： G06F15/78 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a bus operating method capable of easily changing a bus interface specification by increasing effective operation speeds of a bus, and a memory and peripheral function units connected to the bus, in a microcomputer system. SOLUTION: An access operation through buses 113 and 114 with bus masters 101 and 102 connected is executed in a pipeline manner, and control of the pipeline execution is carried out by an exclusive bus controller 111. An access delaying the pipeline operation is executed by buses 123 and 124 of a lower tier connected through a buffer means 112, and by a bus controller 121 exclusively used for the lower tier. Therefore, the bus band for access is improved, and bus interfaces having various specifications, and buses allowing parallel execution can easily be structured. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种总线操作方法，其能够通过在微计算机系统中增加总线的有效操作速度以及连接到总线的存储器和外围功能单元来容易地改变总线接口规范。解决方案：以流水线方式执行通过连接有总线主机101和102的总线113和114的访问操作，并且由专用总线控制器111执行流水线执行的控制。延迟流水线操作的访问是由通过缓冲装置112连接的下层的总线123和124执行，并且由专用于下层的总线控制器121执行。因此，改善了用于访问的总线频带，并且可以容易地构造具有各种规格的总线接口和允许并行执行的总线。版权所有（C）2004，JPO

22. 发明专利

JPH11102286A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JPH11102286A
公开(公告)日：1999-04-13
申请号：JP15814398
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method for division with which a correct quotient can be easily found without detecting whether the partial remainder is '0' or not for each step of division for finding the quotient bit even when a dividend is negative. SOLUTION: When a dividend X is negative in the coded division expressed as Y (quotient) = X (dividend) ÷ 3 (divisor), for example, preprocessing is performed to define a value (X-1) subtracting '1' from the dividend X as a dividend. The preprocessing is processing for conceptionally shifting the coordinate axis of the quotient Y to left for '1'. The processing of division is performed in the shifting state. Thus, it is not necessary to discriminate whether the partial remainder is '0' or not conventionally every time in the middle of arithmetic processing and a hardware for that discrimination is unnecessitated as well. When finding the exact remainder, the found remainder is finally corrected.

23. 发明专利

JPH1196000A CPU AND MICROCOMPUTER 失效
公开(公告)号：JPH1196000A
公开(公告)日：1999-04-09
申请号：JP15814298
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/30 , G06F9/35
摘要： PROBLEM TO BE SOLVED: To prevent the utilization of immediate data or the designation of an absolute address from being limited even when the number of bits of a fixed length instruction format is less than the data word length, by adopting the fixed length instruction format having bits less than the maximum data word length supplied to an instruction executing means. SOLUTION: IRH and IRL are the instruction buffers of 16 bits respectively, and an instruction is transferred through an internal data bus for the unit of 32 bits while being stored one by one. These instructions are loaded through a multiplexer MPX to an instruction register IR1. The instruction register IR1 has 16 bits. Thus, since the fixed length instruction format of 16 bits is adopted for the data word length of 32 bits, the judgement on where an instruction border exists, can be grasped before the completion of the preceding instruction, and the advantage of the simplification of instruction decode processing or the like is guaranteed. Further, the useless arrangement of bits is decreased and the utilization efficiency of a program memory is improved.

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