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21. 发明专利

JP2011160257A Optical transmission circuit and optical communication system 有权
标题翻译：光传输电路和光通信系统
公开(公告)号：JP2011160257A
公开(公告)日：2011-08-18
申请号：JP2010021084
申请日：2010-02-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEMOTO KYOJI , YAMASHITA HIROKI , TSUJI SHINJI
IPC分类号： H04B10/40 , H04B10/07 , H04B10/50 , H04B10/516 , H04B10/58 , H04B10/60 , H04B10/61
CPC分类号： H04B10/58 , H04B10/564
摘要： PROBLEM TO BE SOLVED: To provide an optical transmission circuit and optical communication system capable of making a communication speed high.
SOLUTION: An optical transmission circuit includes, e.g.: a laser diode LD1; a temperature/optical detection circuit block PTDET_BK for detecting a temperature or optical output power of the LD1 and outputting a control signal S_CLTo; a laser driver circuit LDV1a for driving the LD1; and a pre-driver circuit PDV1a positioned on a pre-stage of the laser driver circuit LDV1a. The PDV1a includes: a variable amplifying circuit VAMPp; and a variable offset circuit VOF coupled to output of the variable amplifying circuit VAMPp; wherein an offset amount by the VOF is controlled according to the S_CLTo. By the offset amount by the VOF, nonlinear characteristics of the optical output power in the LD1 are compensated.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够使通信速度高的光传输电路和光通信系统。解决方案：光传输电路包括例如激光二极管LD1; 温度/光检测电路块PTDET_BK，用于检测LD1的温度或光输出功率，并输出控制信号S_CLTo; 用于驱动LD1的激光驱动电路LDV1a; 以及位于激光驱动电路LDV1a的前级的预驱动电路PDV1a。 PDV1a包括：可变放大电路VAMPp; 以及耦合到可变放大电路VAMPp的输出的可变偏移电路VOF; 其中根据S_CLTo控制通过VOF的偏移量。通过VOF的偏移量，LD1中的光输出功率的非线性特性被补偿。版权所有（C）2011，JPO＆INPIT

22. 发明专利

JP2011015149A Waveform equalization circuit with pulse width modulation 有权
标题翻译：波形宽度调制的波形均衡电路
公开(公告)号：JP2011015149A
公开(公告)日：2011-01-20
申请号：JP2009157036
申请日：2009-07-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , FUKUDA KOJI
IPC分类号： H04L25/03 , H04B3/04
CPC分类号： H04B3/04
摘要： PROBLEM TO BE SOLVED: To achieve low power consumption of a waveform equalization circuit with pulse width modulation.SOLUTION: There is provided: pulse width adjustment level generation circuits PWCLC1a and PWCLC2a that generate a pulse width adjustment level VCNT based on previous input data Din_P and Din_N; pulse width adjustment circuits PWCC1a and PWCC2a that adjust the pulse width depending on the VCNT; and a waveform shaping circuit WAC that shapes an output signal waveform from the pulse width adjustment circuits. In the pulse width adjustment circuit, the driving power is controlled according to consecutive bits count of the previous input data, and varies transition time of output data Do2_P and Do2_N to adjust the pulse width. By using such a waveform equalization scheme, power consumption can be reduced due to simplification in circuit configuration, and further, CMOS circuits can keep the power small.
摘要翻译：要解决的问题：实现具有脉冲宽度调制的波形均衡电路的低功耗。提供：脉冲宽度调整电平生成电路PWCLC1a和PWCLC2a，其基于先前的输入数据Din_P生成脉宽调整电平VCNT， Din_N; 脉冲宽度调节电路PWCC1a和PWCC2a，根据VCNT调节脉冲宽度; 以及波形整形电路WAC，其对来自脉冲宽度调整电路的输出信号波形进行整形。在脉冲宽度调整电路中，根据先前输入数据的连续比特数来控制驱动功率，并且改变输出数据Do2_P和Do2_N的转换时间以调整脉冲宽度。通过使用这样的波形均衡方案，由于电路结构的简化，能够降低功耗，进一步地，CMOS电路可以保持功率小。

23. 发明专利

JP2009038542A Oscillation circuit 审中-公开
标题翻译：振荡电路
公开(公告)号：JP2009038542A
公开(公告)日：2009-02-19
申请号：JP2007200351
申请日：2007-08-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , FUKUDA KOJI , NEMOTO AKIRA , KANAI HISAAKI , YAMAMOTO KEIICHI
IPC分类号： H03K3/03 , H03K3/0231 , H03K3/354 , H03K5/00 , H03L7/099
CPC分类号： H03K3/0322
摘要： PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of generating a highly precise clock signal with small variations. SOLUTION: The oscillation circuit includes a plurality of ring oscillator portions RO1 and RO2 containing an inverter circuit IV of odd stages and a summing portion ADD for adding a signal of output nodes RO_O1 and RO_O2 of the RO1 and the RO2. Then, while outputting the summed result of the ADD from an output node OSC_O as a clock signal, the output node OSC_O is fed back to input nodes RO_I1 and RO_I2 of the RO1 and the RO2. Thereby, if a delay time of the RO1 and the RO2 varies based on normal distribution of standard deviation σ respectively, for example, variations in clock signals obtained from OSC_O can be set to σ/√2. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够产生具有小变化的高精度时钟信号的振荡电路。解决方案：振荡电路包括包含奇数级的反相器电路IV的多个环形振荡器部分RO1和RO2以及用于将RO1和RO2的输出节点RO_O1和RO_O2的信号相加的求和部分ADD。然后，当从输出节点OSC_O输出ADD的求和结果作为时钟信号时，输出节点OSC_O被反馈到RO1和RO2的输入节点RO_I1和RO_I2。因此，如果RO1和RO2的延迟时间分别基于标准偏差σ的正态分布而变化，例如，可以将从OSC_O获得的时钟信号的变化设置为σ/√2。版权所有（C）2009，JPO＆INPIT

24. 发明专利

JP2008271459A Semiconductor device with transmission/reception circuit between circuit blocks 有权
标题翻译：具有电路块之间的传输/接收电路的半导体器件
公开(公告)号：JP2008271459A
公开(公告)日：2008-11-06
申请号：JP2007115001
申请日：2007-04-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , NEMOTO AKIRA
IPC分类号： H04L25/02 , H03K19/0175
CPC分类号： H03K19/018557
摘要： PROBLEM TO BE SOLVED: To provide an inter-block transmission/reception circuit that achieves stable signal transmission by suppressing variation of a current signal caused by variation of wiring resistance in transmission of inter-block wiring on a semiconductor substrate.
SOLUTION: A receiving circuit includes first and second constant current source means connected to a pair of first and second receiving terminals receiving complementary current signals, a first NMOS transistor of which a source is connected to the first receiving terminal and the first constant current source means and of which a drain is connected to a first power source via a first output terminal and a first resistance means, and a second NMOS transistor of which a source is connected to the other second receiving terminal and the second constant current source means and of which a drain is connected to the first power source via a second output terminal and a second resistance means, wherein a gate voltage of the second NMOS transistor is controlled by a voltage signal of in-phase with a voltage signal of the first output terminal and a gate voltage of the first NMOS transistor is controlled by a voltage signal of in-phase with a voltage signal of the second output terminal.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种通过抑制由半导体衬底上的块间布线的透射中的布线电阻的变化引起的电流信号的变化来实现稳定的信号传输的块间发送/接收电路。解决方案：接收电路包括连接到接收互补电流信号的一对第一和第二接收端的第一和第二恒流源装置，源极连接到第一接收端的第一NMOS晶体管和第一恒定电流源电流源装置，其漏极经由第一输出端子和第一电阻装置连接到第一电源，以及第二NMOS晶体管，源极连接到另一第二接收端子，第二恒流源装置并且其漏极经由第二输出端子和第二电阻装置连接到第一电源，其中第二NMOS晶体管的栅极电压由与第一输出的电压信号同相的电压信号控制并且第一NMOS晶体管的栅极电压由与第二输出端子的电压信号同相的电压信号控制。版权所有（C）2009，JPO＆INPIT

25. 发明专利

JP2008066908A Equalization pulse width control circuit 有权
标题翻译：均衡脉冲宽度控制电路
公开(公告)号：JP2008066908A
公开(公告)日：2008-03-21
申请号：JP2006240941
申请日：2006-09-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUKUDA KOJI , TOYODA HIDEHIRO , YAMASHITA HIROKI
IPC分类号： H04L25/49 , H04B3/04
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10194 , G11B20/10481 , G11B2220/2537
摘要： PROBLEM TO BE SOLVED: To provide an equalization pulse width control circuit in which the circuit scale of a transmission side required for suppressing pattern jitters due to intersymbol interference can be reduced and which enables the time and labor of the training of the circuit to be substantially shortened.
SOLUTION: In equalization pulse width control, attention is paid to the presence/absence of the symmetry of early and late signals, and the size of a table for storing the adjustment amount of an edge position is reduced to the 1/2 power. To put it concretely, the pulse time width of each symbol is adjusted to an optimum pulse width determined by a computational expression or table retrieval in accordance with a symbol sequence to be transmitted. In the configuration of using the table, the table is prepared for storing the edge position adjustment amount with the column of the exclusive OR of two symbols at early and late symmetrical positions centering on a symbol to be just sent out in the symbol sequence as a retrieval key.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种均衡脉冲宽度控制电路，其中可以减少由于符号间干扰而导致的抑制模式抖动所需的发送侧的电路规模，并且能够使电路的训练花费时间和精力大大缩短。解决方案：在均衡脉冲宽度控制中，注意早期和晚期信号的对称性的存在/不存在，并且用于存储边缘位置的调节量的表的尺寸减小到1/2 功率。具体而言，将每个符号的脉冲时间宽度根据要发送的符号序列调整到由计算表达式或表检索确定的最佳脉冲宽度。在使用表格的结构中，准备表格，用于存储边缘位置调整量与以两个符号的异或的列为中心的符号的早和中对称位置，以便以符号顺序发送为一个检索关键字。版权所有（C）2008，JPO＆INPIT

26. 发明专利

JP2005267700A Semiconductor integrated circuit and magnetic storage device using it 有权
标题翻译：半导体集成电路和使用它的磁存储器件
公开(公告)号：JP2005267700A
公开(公告)日：2005-09-29
申请号：JP2004075526
申请日：2004-03-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , YAGYU MASAYOSHI , YUKI FUMIO , KAWASHITA TATSUYA
IPC分类号： G11B5/09 , G11B5/00 , G11B5/012 , G11B5/02 , G11B5/39 , G11C16/06 , H03K17/00 , H03K17/687
CPC分类号： G11B5/02 , B82Y10/00 , B82Y25/00 , G11B5/022 , G11B2005/0013 , G11B2005/3996 , H03K17/6872 , H03K2217/0036
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which enables the reduction of a circuit space, and a magnetic storage device using it.
SOLUTION: The semiconductor integrated circuit includes; an output transistor MN200 of a single stage configuration which supplies a write current nIw to a magnetic head 1; a current source 22 which outputs a current Iw to be used as a reference of the write current nIw; an NMOS transistor MN202 of diode connection which converts the current Iw to the gate voltage and is equipped with a constant element size ratio to the output transistor MN200; a regulator circuit 21 which transmits gate voltage of the NMOS transistor MN202, and makes the output impedance small; and a CMOS circuit 20 which makes the output of the regulator circuit 21 power source voltage and controls a gate voltage of the output transistor. These circuits are applied as write circuits of the magnetic storage device.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够减少电路空间的半导体集成电路和使用该半导体集成电路的磁存储装置。解决方案：半导体集成电路包括：向磁头1提供写入电流nIw的单级结构的输出晶体管MN200; 输出用作写入电流nIw的基准的电流Iw的电流源22; 二极管连接的NMOS晶体管MN202，其将电流Iw转换为栅极电压，并且与输出晶体管MN200配备有恒定的元件尺寸比; 调节电路21，其传输NMOS晶体管MN202的栅极电压，并使输出阻抗较小; 以及CMOS电路20，其使调节器电路21的输出电源电压并控制输出晶体管的栅极电压。这些电路被用作磁存储装置的写入电路。版权所有（C）2005，JPO＆NCIPI

27. 发明专利

JP2005101993A Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：JP2005101993A
公开(公告)日：2005-04-14
申请号：JP2003334368
申请日：2003-09-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , KOYAMA AKIO , AIDA SHINYO , ITO ATSUSHI , SONEHARA MICHIHITO
IPC分类号： H03K19/086 , H03F1/30 , H03F3/45 , H03K5/22 , H03K19/003 , H03K19/0944
CPC分类号： H03K19/00369 , H03F1/301 , H03K19/09448
摘要： PROBLEM TO BE SOLVED: To cut dependence on a power supply voltage of a current switch current and to lower the power supply voltage.
SOLUTION: The logic circuit includes an emitter-coupled logic circuit 118 and a reference voltage generating circuit 119 which generates a reference voltage VCSC for controlling a drain current (= current switch current ICS) of an n-type MOS transistor 110 for a current generator. The emitter-coupled logic circuit 118 includes a current switch which is composed of an emitter-coupled pair of bipolar transistors 106 and 107, the n-type MOS transistor 110 for a current generator which is connected in series with the current switch and resistor means 108 and 109 which are respectively connected in series with the bipolar transistor 106 and 107 for taking out an output voltage. The reference voltage generating circuit 119 includes an n-type MOS transistor 111, a bipolar transistor 112 which determines the drain voltage of the n-type MOS transistor 111 and a control circuit 120 which controls the drain current of the n-type MOS transistor 111.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：减少对电流开关电流的电源电压的依赖性并降低电源电压。解决方案：逻辑电路包括发射极耦合逻辑电路118和参考电压产生电路119，其产生用于控制n型MOS晶体管110的漏极电流（=电流开关电流ICS）的参考电压VCSC，用于电流发生器。发射极耦合逻辑电路118包括由发射极耦合的双极晶体管106和107组成的电流开关，用于与电流开关串联连接的电流发生器的n型MOS晶体管110和电阻器装置 108和109分别与双极晶体管106和107串联连接以取出输出电压。参考电压发生电路119包括n型MOS晶体管111，确定n型MOS晶体管111的漏极电压的双极晶体管112和控制n型MOS晶体管111的漏极电流的控制电路120 （C）2005，JPO＆NCIPI

28. 发明专利

JP2003204369A SIGNAL TRANSMISSION/RECEPTION APPARATUS, CIRCUIT AND LOOP- BACK TEST METHOD 审中-公开
公开(公告)号：JP2003204369A
公开(公告)日：2003-07-18
申请号：JP2002001900
申请日：2002-01-09
申请人： HITACHI LTD
发明人： BABA TAKANARI , SAITO TATSUYA , YAMASHITA HIROKI , TAKEUCHI YUSUKE , ISOMURA SATORU
IPC分类号： G01R31/28 , H04L1/24 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To provide an apparatus in which mounting cost and power consumption are reduced by reducing the number of high-speed signal lines connecting a group of transmission circuits to a group of reception circuits which are necessary, in performing a loop-back test of a signal transmission/reception apparatus for signal communication. SOLUTION: Reference numeral 101 denotes a communication apparatus A for transmitting/receiving a parallel signal, reference numeral 103 denotes a communication apparatus B for transmitting/receiving a serial signal, and a reference numeral 102 denotes a signal transmission/reception apparatus provided between the apparatuses 101 and 103 to convert the parallel signal to the serial signal and vice versa. The apparatus 102 consists of a transmission circuit IC 104 and a reception circuit IC 108. The IC 104 comprises a serializer 105 and a transmission driver 107, and the IC 108 comprises an input buffer 111 and a deserializer 109. COPYRIGHT: (C)2003,JPO

29. 发明专利

JP2001051957A ON-CHIP MULTIPLEXER 失效
公开(公告)号：JP2001051957A
公开(公告)日：2001-02-23
申请号：JP22172899
申请日：1999-08-04
申请人： HITACHI LTD
发明人： KATO TAKESHI , YAMAMOTO MICHITAKA , KAINO HIROMICHI , SHIMIZU TERUHISA , OBAYASHI MASAYUKI , YAMASHITA HIROKI , MASUDA NOBORU , SAITO TATSUYA
IPC分类号： G06F15/16 , G06F15/00 , G06F15/80
摘要： PROBLEM TO BE SOLVED: To make control between multiple processor fast and high in performance by arranging a couple of processors among the processors symmetrically about a specific straight axis or specific origin on a chip plane. SOLUTION: An instruction processor IP10 and IP20 are arranged symmetrically about a virtual straight axis 40 on the chip plane and further an SU 30 of a storage control unit is arranged in an area containing the straight axis 40. Further, GSs 32, 33 as common caches of the instruction processor IP10, IP20 and common I/Os 34, 35 of the IPs 10 and 20 are arranged symmetrically about the straight axis 40 and also symmetrically about a straight axis 41. Further, double units have instruction units IUs 11, 12 and IUs 21, 22, general arithmetic unit GUs 14, 15 and GUs 24, 25, and floating-point unit FUs 16, 17 and FUs 26, 27 arranged symmetrically about the straight axis 41.

30. 发明专利

JPH11355119A ELC-CMOS LEVEL CONVERSION CIRCUIT AND CONTROL SIGNAL GENERATION CIRCUIT 失效
公开(公告)号：JPH11355119A
公开(公告)日：1999-12-24
申请号：JP15714198
申请日：1998-06-05
申请人： HITACHI LTD
发明人： TANAKA KATSUYA , YAMASHITA HIROKI
IPC分类号： H03K19/0175
摘要： PROBLEM TO BE SOLVED: To realize a high speed operation by connecting a differential amplifier to a positive power source, and setting the effective voltage value of a voltage drop means so that the output voltage of the differential amplifier when the input signals of same voltage are inputted to the first input terminal and the second input terminal of the differential amplifier becomes equal to the threshold voltage of a first CMOS inverter circuit. SOLUTION: The base of a bipolar transistor Tr1 is connected to an input terminal IN and the base of a bipolar transistor Tr2 is connected to bias VBB. The base of a bipolar transistor Tr5 is connected to bias VCS and the emitter of the transistor Tr5 is connected to a power source VEE through a resistance R3. The transistor Tr5 and the resistance R3 operate as low current sources making current values flow. A P-type MOS transistor Tr3 and an N-type MOS transistor Tr4 constitute a CMOS inverter INV1. The signal of an ECL level is inputted to the input terminal IN and the inverter INV1 is driven.

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