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11. 发明专利

JP2008270365A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008270365A
公开(公告)日：2008-11-06
申请号：JP2007108544
申请日：2007-04-17
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： MIYAGI KYOSUKE , SAITO HIROKAZU , HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a technique for improving a breakdown voltage in a semiconductor device, where a buried insulator is formed at a deep section in a trench, an insulating layer is formed on the wall surface of a shallow section in the trench, and the inside of the insulating layer is filled with a trench inner conductor.
SOLUTION: The trench T has a shallow trench 30a having width L1, a deep trench 40 having width L2 (L2
摘要翻译：要解决的问题：为了提供一种在沟槽的深部形成埋入式绝缘体的半导体装置中的击穿电压的技术，在浅层的壁部的壁面上形成有绝缘层沟槽，并且绝缘层的内部填充有沟槽内导体。解决方案：沟槽T具有宽度为L1的浅沟槽30a，具有宽度L2（L2

12. 发明专利

JP2007287972A Stencil mask 有权
标题翻译： STENCIL MASK
公开(公告)号：JP2007287972A
公开(公告)日：2007-11-01
申请号：JP2006114381
申请日：2006-04-18
申请人： Toyota Motor Corp , Ulvac Japan Ltd , トヨタ自動車株式会社 , 株式会社アルバック
发明人： NISHIWAKI TAKESHI , SAITO HIROKAZU , NISHIBASHI TSUTOMU , TONARI KAZUHIKO
IPC分类号： H01L21/027 , G03F1/20 , H01L21/266
摘要： PROBLEM TO BE SOLVED: To provide a stencil mask having through-holes for forming a variety of irradiation regions in which a desired region on the surface of a semiconductor substrate is irradiated with ionized atoms having passed through the through-hole with high coincidence. SOLUTION: The stencil mask 10 has a backside layer 50 on the side where a semiconductor substrate is arranged, a surface layer 20 on the incident side of ionized atoms, and an intermediate layer 30 provided between the backside layer 50 and the surface layer 20. Third through-holes 52 and 56 having a profile corresponding to a predetermined region are formed in the backside layer 50. Second through-holes 32 and 36 communicating with the third through-holes 52 and 56 are formed in the intermediate layer 30. In a range of the surface layer 20 corresponding to at least one round second through-holes 32, a plurality of first through-holes 22 communicating with that round second through-holes 32 are formed while being dispersed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有用于形成各种照射区域的通孔的模板掩模，其中半导体衬底的表面上的期望区域被具有高通量的通孔的电离原子照射巧合。解决方案：模板掩模10在其上布置半导体衬底的一侧上具有背面层50，在电离原子的入射侧具有表面层20，以及设置在背面层50和表面之间的中间层30 在背面层50中形成具有对应于预定区域的轮廓的第三通孔52和56.在中间层30中形成与第三通孔52和56连通的第二通孔32和36 在对应于至少一个圆形第二通孔32的表面层20的范围内，形成与该圆形第二通孔32连通的多个第一通孔22，并分散。版权所有（C）2008，JPO＆INPIT

13. 发明专利

JP2010192597A Semiconductor device, switching device, and method of controlling semiconductor device 有权
标题翻译：半导体器件，开关器件和控制半导体器件的方法
公开(公告)号：JP2010192597A
公开(公告)日：2010-09-02
申请号：JP2009034047
申请日：2009-02-17
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： MIYAGI KYOSUKE , SAITO HIROKAZU , SOENO AKITAKA , YAMADA TETSUYA , IKEDA TOMOHARU
IPC分类号： H01L27/04 , H01L21/8234 , H01L27/088 , H01L29/739 , H01L29/78 , H02M7/48
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an IGBT which has a low ON voltage and a diode which has low reverse recovery loss.
SOLUTION: The semiconductor device includes a semiconductor substrate which has an upper electrode formed on an upper surface and a lower electrode formed on a lower surface, and also has a vertical IGBT and a vertical diode formed. The IGBT has an n-type emitter region, a p-type body region, an n-type drift region, a p-type collector region, and a gate electrode opposed to the body region, within a range wherein the emitter region and drift region are isolated, with an insulating film interposed. The diode has a p-type anode region, an n-type cathode region continuous with the drift region, and a control electrode opposed to the cathode region with the insulating film interposed. Within a range wherein the cathode region comes into contact with the insulating film, a high-concentration region is formed, which has a higher n-type impurity concentration than the cathode region at the periphery thereof.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有低导通电压的IGBT和具有低反向恢复损耗的二极管的半导体器件。解决方案：半导体器件包括具有形成在上表面上的上电极和形成在下表面上的下电极的半导体衬底，并且还形成有垂直IGBT和垂直二极管。 IGBT在其发射极区域和漂移区域的范围内具有n型发射极区域，p型体区域，n型漂移区域，p型集电极区域和与体区域相对的栅极电极区域隔离，绝缘膜插入。二极管具有p型阳极区域，与漂移区域连续的n型阴极区域和与阴极区域相对的绝缘膜的控制电极。在阴极区域与绝缘膜接触的范围内，形成高浓度区域，其在其周围具有比阴极区域更高的n型杂质浓度。版权所有（C）2010，JPO＆INPIT

14. 发明专利

JP2007208095A Stencil mask 审中-公开
标题翻译： STENCIL MASK
公开(公告)号：JP2007208095A
公开(公告)日：2007-08-16
申请号：JP2006026642
申请日：2006-02-03
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： NISHIWAKI TAKESHI , SAITO HIROKAZU
IPC分类号： H01L21/027 , G03F1/20 , G03F1/40 , H01J37/305 , H01L21/266
摘要： PROBLEM TO BE SOLVED: To suppress a collision phenomenon of a charged particle to the side wall of a stencil mask by increasing electric field strength based on an electric potential distribution formed at the periphery of the stencil mask. SOLUTION: The stencil mask 10 comprises a first conductive layer 22, a first insulating layer 24 formed on the layer 22, and a second conductive layer 26 formed on the layer 24. The stencil mask 10 is further formed on the outer surface of the layer 22 or the layer 26, and comprises connection parts 32, 34 connected to power supplies 42, 44. A through-hole 28 for making the layers 22, 24 and 26 penetrate therethough is formed in the stencil mask 10 corresponding to a predetermined pattern. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过基于在模板掩模的周边形成的电位分布来增加电场强度来抑制带电粒子与模板掩模的侧壁的碰撞现象。解决方案：模板掩模10包括第一导电层22，形成在层22上的第一绝缘层24和形成在层24上的第二导电层26.模板掩模10还形成在外表面层22或层26，并且包括连接到电源42,44的连接部分32,34。用于使层22,24和26穿透的通孔28形成在模板掩模10中，对应于预定模式。版权所有（C）2007，JPO＆INPIT

15. 发明专利

JP2009054638A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009054638A
公开(公告)日：2009-03-12
申请号：JP2007217401
申请日：2007-08-23
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： HISANAGA YUKIHIRO , SAITO HIROKAZU , MIYAGI KYOSUKE
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a technique for improving the breakdown voltage of a semiconductor device having a structure where a buried insulator is formed at a bottom section of a trench, and insulating films are formed on both side surfaces of a shallow section of the trench not filled with the buried insulator.
SOLUTION: The trench T which extends from a surface 11a of a semiconductor layer 11 along the depth is formed in the semiconductor layer 11, the buried insulator 44 is charged in a deep area of the trench T, and both side surfaces 31 of the trench T in the shallow region not charged with the buried insulator 44 are covered with heat oxide films 32; an in-trench conductor 36 is charged in inside area between the two heat oxide films 32 facing each other at an interval of a trench width, and the center line 32a of the film thickness H of each heat oxide film 32 moves away from the center line M of the trench width nearby an area of contact with the buried insulator 44 as it approaches the surface 11a of the semiconductor layer 11.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于提高具有在沟槽的底部形成有埋入绝缘体的结构的半导体器件的击穿电压的技术，并且在浅的两个表面上形成绝缘膜沟槽部分没有埋入埋地绝缘子。解决方案：从半导体层11的表面11a沿深度延伸的沟槽T形成在半导体层11中，埋入绝缘体44被填充在沟槽T的深部区域中，并且两个侧表面31 在没有埋入绝缘体44的浅区域中的沟槽T被热氧化膜32覆盖; 在沟槽宽度的间隔彼此面对的两个热氧化膜32之间的内部区域中充填沟槽状导体36，并且每个热氧化膜32的膜厚度H的中心线32a远离中心沟槽宽度的线M在接近半导体层11的表面11a时与埋入绝缘体44接触的区域附近。（C）2009，JPO＆INPIT

16. 发明专利

JP2009026809A Semiconductor apparatus and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009026809A
公开(公告)日：2009-02-05
申请号：JP2007185789
申请日：2007-07-17
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： MIYAGI KYOSUKE , SAITO HIROKAZU , HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a technique for improving the breakdown voltage of a semiconductor apparatus configured so that a buried insulator is formed at a deep portion of a trench, an insulating layer is formed on a side wall of a shallow portion of the trench, and an in-trench conductor is charged inside the insulating layer.
SOLUTION: In the trench T formed from a surface 11a of a silicon semiconductor layer along the depth, there are formed a thermally oxidized silicon layer 32 covering an internal surface of the trench T, a silicon nitride layer 43 covering an internal surface 32a of the thermally oxidized silicon layer 32 at the deep portion of the trench T, the buried insulator 44 charged in the deep portion of the trench T where the internal surface 32a of the thermally oxidized silicon layer 32 is covered with the silicon nitride layer 43, and the in-trench conductor 36 charged in the shallow portion of the trench T where the internal surface 32a of the thermally oxidized silicon layer 32 is not covered with the silicon nitride layer 43.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于提高半导体装置的击穿电压的技术，该半导体装置被构造为在沟槽的深部形成埋入绝缘体，在浅部的侧壁上形成绝缘层并且沟槽内导体被填充在绝缘层内部。解决方案：在沿着深度从硅半导体层的表面11a形成的沟槽T中，形成覆盖沟槽T的内表面的热氧化硅层32，覆盖内表面的氮化硅层43 在沟槽T的深部的热氧化硅层32的32a，埋入绝缘体44，其被填充在沟槽T的深部，热氧化硅层32的内表面32a被氮化硅层43覆盖以及填充在沟槽T的浅部的沟槽内导体36，其中热氧化硅层32的内表面32a未被氮化硅层43覆盖。版权所有（C）2009，JPO＆INPIT

17. 发明专利

JP2008270487A Method of manufacturing semiconductor wafer and semiconductor chip 有权
标题翻译：制造半导体滤波器和半导体芯片的方法
公开(公告)号：JP2008270487A
公开(公告)日：2008-11-06
申请号：JP2007110743
申请日：2007-04-19
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： MIYAGI KYOSUKE , SAITO HIROKAZU , NISHIWAKI TAKESHI
IPC分类号： H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor wafer capable of reducing the amount of warpage in the wafer. SOLUTION: One portion of the semiconductor wafer 10 is divided into a plurality of square blocks. The plurality of blocks are arranged in the semiconductor wafer in grids, and a plurality of chips 12 having a common thickness are formed in respective blocks. On the surface of the semiconductor wafer 10, the surface of one of adjacent blocks is more recessed than that of the other block. On the rear surface of the semiconductor wafer 10, the rear surface of one of adjacent blocks is more protruded than that of the other. Height of a recessed and projecting part on the front equals that of a recessed and projecting part on the rear. The amount of warpage in the semiconductor wafer 10 is inversely proportional to the third power of the sum of the wafer thickness in each block and the height of an uneven surface, thus greatly reducing the amount of warpage. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少晶片翘曲量的半导体晶片。解决方案：半导体晶片10的一部分被分成多个方块。多个块被布置在栅格中的半导体晶片中，并且在各个块中形成具有共同厚度的多个芯片12。在半导体晶片10的表面上，相邻块之一的表面比另一个块的表面更凹陷。在半导体晶片10的后表面上，相邻块之一的后表面比另一块的后表面更突出。前部的凹凸部的高度等于后方的凹凸部的高度。半导体晶片10中的翘曲量与各块中的晶片厚度之和的第三功率与不平坦表面的高度成反比，从而大大减少翘曲量。版权所有（C）2009，JPO＆INPIT

18. 发明专利

JP2011210973A Semiconductor device manufacturing apparatus and method of manufacturing semiconductor device 有权
标题翻译：半导体器件制造装置及制造半导体器件的方法
公开(公告)号：JP2011210973A
公开(公告)日：2011-10-20
申请号：JP2010077632
申请日：2010-03-30
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： ONOKI ATSUSHI , YAMADA TETSUYA , SAITO HIROKAZU
IPC分类号： H01L21/301
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing apparatus capable of improving reliability and yield of a semiconductor device by suppressing adhesion and the like of fragments and the like which may be produced at dicing, and a method of manufacturing a semiconductor device.SOLUTION: The semiconductor device manufacturing apparatus manufactures a semiconductor device by dicing a semiconductor wafer in which a plurality of semiconductor device elements are formed, wherein boundary regions of the device elements are modified or worked. The manufacturing apparatus includes a freely rotatable rotating table and a plurality of pedestals loaded on the rotating table and movable in the radial direction. A semiconductor wafer is fixed on one of the surfaces of a stretchable sheet member whose size is larger than the semiconductor wafer when planely viewed, and the sheet member is fixed to the plurality of pedestals. By rotating the rotating table to move the plurality of pedestals outward in the radial direction by the centrifugal force, the sheet member is extended in the radial direction, and thereby the semiconductor wafer fixed on the sheet member is diced into individual device elements.
摘要翻译：要解决的问题：提供一种能够通过抑制在切割时可能产生的碎片等的粘附等来提高半导体器件的可靠性和产率的半导体器件制造装置，以及制造半导体器件的方法。：半导体器件制造装置通过切割形成有多个半导体器件元件的半导体晶片来制造半导体器件，其中器件元件的边界区域被修改或加工。该制造装置包括可旋转的旋转台和装载在旋转台上并可在径向方向上移动的多个基座。当平面观察时，半导体晶片固定在尺寸大于半导体晶片的可拉伸片材的一个表面上，并且片状构件固定到多个基座。通过旋转旋转台，通过离心力使多个基座向径向外侧移动，片材在径向方向上延伸，由此将固定在片状构件上的半导体晶片切割成单独的元件。

19. 发明专利

JP2010263149A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010263149A
公开(公告)日：2010-11-18
申请号：JP2009114729
申请日：2009-05-11
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： YAMADA TETSUYA , MIYAGI KYOSUKE , IKEDA TOMOHARU , SAITO HIROKAZU
IPC分类号： H01L27/04 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves both reducuction of resistance of an IGBT and recovery characteristics of an FWD.
SOLUTION: The semiconductor device includes the IGBT formed in a first region in a semiconductor layer, including a first trench region, a first gate formed in the first trench region, and an emitter and a collector arranged apart from each other along the thickness of the semiconductor layer, and controlling a current flowing along the thickness of the semiconductor layer by controlling the potential of the first gate; and the FWD formed in a second region adjacent to the first region in the semiconductor layer, including a second trench region, a second gate formed in the second trench region, a base and a collector arranged apart from each other along the thickness of the semiconductor layer, a crystal defect region or lifetime control region formed at a bottom of the second trench and having its potential controlled by the second gate. When the FWD is off, the potential of the second gate is controlled to gather residual carriers in the semiconductor layer to the crystal defect region or lifetime control region.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现IGBT的电阻的降低和FWD的恢复特性的半导体器件。解决方案：半导体器件包括形成在半导体层中的第一区域中的IGBT，包括第一沟槽区域，形成在第一沟槽区域中的第一栅极和沿着第一沟槽区域彼此分离布置的发射极和集电极并且通过控制第一栅极的电位来控制沿着半导体层的厚度流动的电流; 并且所述FWD形成在与所述半导体层中的与所述第一区域相邻的第二区域中，包括第二沟槽区域，形成在所述第二沟槽区域中的第二栅极，沿着所述半导体的厚度彼此分离布置的基极和集电极层，形成在第二沟槽的底部并具有由第二栅极控制的电位的晶体缺陷区域或寿命控制区域。当FWD关闭时，控制第二栅极的电位以将半导体层中的残留载流子收集到晶体缺陷区域或寿命控制区域。版权所有（C）2011，JPO＆INPIT

20. 发明专利

JP2009021393A Beam irradiating method and beam irradiating device 审中-公开
标题翻译：光束辐射方法和光束辐射装置
公开(公告)号：JP2009021393A
公开(公告)日：2009-01-29
申请号：JP2007182767
申请日：2007-07-12
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： NISHIWAKI TAKESHI , SAITO HIROKAZU
IPC分类号： H01L21/027 , H01J37/305
摘要： PROBLEM TO BE SOLVED: To provide a beam irradiating method and a beam irradiating device that can irradiate a semiconductor wafer with a beam while adjusting the wafer and a mask to be parallel.
SOLUTION: At least three capacitor electrodes 24 are formed on a surface 8b of a stencil mask which is disposed opposite the semiconductor wafer 44 with an insulating layer 6 interposed therebetween, and electrostatic capacity between each capacitor electrode 24 and the semiconductor wafer 44 is measured using a measuring means 28. The electrostatic capacity depends upon the area of the capacitor electrode 24 and the distance between the capacitor electrode 24 and the semiconductor wafer 44, and the ratio of distances between the capacitor electrodes 24 and semiconductor wafer 44 at at least three places can be found from measurement results of the measuring means 28 when the area ratio of the capacitor electrodes 24 is known. A tilt of a sample stage 42 is adjusted using an adjusting means 40 so that the ratio of the distances becomes "1", and thus making the stencil mask 8 and semiconductor wafer 44 parallel to each other.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在调整晶片和掩模平行的同时用光束照射半导体晶片的光束照射方法和光束照射装置。解决方案：在模板掩模的表面8b上形成至少三个电容器电极24，该模板掩模的表面8b与半导体晶片44相对设置有绝缘层6，并且每个电容器电极24和半导体晶片44之间的静电电容使用测量装置28测量。静电电容取决于电容器电极24的面积以及电容器电极24和半导体晶片44之间的距离，以及电容器电极24和半导体晶片44之间在距离当电容器电极24的面积比已知时，可以从测量装置28的测量结果中找到至少三个位置。使用调节装置40调整样品台42的倾斜度，使得距离的比例变为“1”，从而使得模版掩模8和半导体晶片44彼此平行。版权所有（C）2009，JPO＆INPIT

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