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11. 发明专利

JP2012119033A Memory system 审中-公开
标题翻译：记忆系统
公开(公告)号：JP2012119033A
公开(公告)日：2012-06-21
申请号：JP2010267828
申请日：2010-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KASHIWAGI HITOSHI , FUJITA SHIRO , WATANABE TOSHIFUMI
IPC分类号： G11C11/413
CPC分类号： G11C16/0483 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To provide a memory system capable of reading data out fast.SOLUTION: The memory system includes: a plurality of banks each having a memory cell array and a sense amplifier; a buffer circuit electrically connected to the banks through a data bus; a switch circuit which changes electric connections between the plurality of bank and the buffer circuit, an interface electrically connected to the buffer circuit; and a control part which controls the banks, buffer circuit, switch circuit, and interface. When data held in the memory cell array is output to the interface with five clocks, the control part controls the switch circuit to electrically connect the banks and the buffer circuit after the clocks are input to the banks and 1.5 clocks elapses, and outputs the data read out of the banks to a burst buffer.
摘要翻译：要解决的问题：提供能够快速读取数据的存储器系统。存储器系统包括：多个存储体，每个存储体具有存储单元阵列和读出放大器; 缓冲电路，通过数据总线电连接到组; 改变多个存储体和缓冲电路之间的电连接的开关电路，电连接到缓冲电路的接口; 以及控制部件，缓冲电路，开关电路和接口的控制部件。当保存在存储单元阵列中的数据以五个时钟输出到接口时，控制部分控制开关电路在时钟被输入到存储体之后电连接存储体和缓冲电路，并经过1.5个时钟，并输出数据从银行读出一个突发缓冲区。版权所有（C）2012，JPO＆INPIT

12. 发明专利

JP2011023085A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011023085A
公开(公告)日：2011-02-03
申请号：JP2009169255
申请日：2009-07-17
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE TOSHIFUMI , ISHIGURO SHIGEFUMI , HAMANO TOMOYUKI , UEHARA KAZUTO
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C8/12 , G11C11/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which increases the speed of synchronization. SOLUTION: The semiconductor memory device has a BootRAM having a first number of banks, DataRAM having a second number of banks which is larger than the first number of banks, and an equalizing timer control circuit 42 that controls pre-charge operation performed for a bit line provided at the BootRAM and the DataRAM. When the BootRAM is synchronized with clock, the equalizing timer control circuit 42 changes an operation time for a second pre-charge operation different from that for a first pre-charge operation after receiving an address ADD, between completion of an initial first pre-charge operation and start of the next second pre-charge operation. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种增加同步速度的半导体存储器件。解决方案：半导体存储器件具有具有第一数量的存储体的BootRAM，DataRAM具有大于第一数量的存储体的第二数量的存储体;以及均衡定时器控制电路42，其控制执行的预充电操作对于BootRAM和DataRAM提供的位线。当BootRAM与时钟同步时，均衡定时器控制电路42在接收到地址ADD之后，在完成初始的第一预充电之后，改变与第一预充电操作不同的第二预充电操作的操作时间操作和开始下一个第二次预充电操作。版权所有（C）2011，JPO＆INPIT

13. 发明专利

JP2012169004A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2012169004A
公开(公告)日：2012-09-06
申请号：JP2011028664
申请日：2011-02-14
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE TOSHIFUMI , SAITO SAKATOSHI
IPC分类号： G11C16/06
CPC分类号： G11C7/222 , G11C16/10 , G11C16/32
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of performing high-speed operation.SOLUTION: In the semiconductor storage device, a first input circuit 105 outputs a first active internal signal in response to the fact that the semiconductor storage device receives a first active control signal. A second input circuit 102 outputs a second active internal signal in response to the fact that the semiconductor storage device receives a second active control signal while the first active control signal is being input to the semiconductor storage device. A delay circuit 106 outputs each of selection signals in the first and second states after the lapse of a predetermined time from a time when the first control signal is made inactive and active. A selection circuit 107 outputs each of the first and second internal signals as enable signals while receiving the first selection signals in the first and second states. A third input circuit 108 outputs an input signal to be input from the outside of the semiconductor storage device from an interface to the inner part of the semiconductor storage device while receiving the active enable signals.
摘要翻译：要解决的问题：提供能够执行高速操作的半导体存储装置。解决方案：在半导体存储装置中，第一输入电路105响应于半导体存储装置接收到第一主动控制信号的事实输出第一有效内部信号。第二输入电路102响应于当第一有源控制信号被输入到半导体存储装置时半导体存储装置接收到第二有源控制信号的事实而输出第二有效内部信号。延迟电路106在从第一控制信号无效并且有效的时间起经过预定时间之后，输出处于第一和第二状态的每个选择信号。选择电路107将第一和第二内部信号中的每一个作为使能信号输出，同时接收第一和第二状态的第一选择信号。第三输入电路108在接收到有效使能信号的同时，将从半导体存储装置的外部输入的输入信号从接口输出到半导体存储装置的内部。版权所有（C）2012，JPO＆INPIT

14. 发明专利

JP2012098837A Memory system 有权
标题翻译：记忆系统
公开(公告)号：JP2012098837A
公开(公告)日：2012-05-24
申请号：JP2010244659
申请日：2010-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SANO YUTA , WATANABE TOSHIFUMI
IPC分类号： G06F13/16 , G11C16/04 , G11C16/06
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/32
摘要： PROBLEM TO BE SOLVED: To provide a memory system that outputs data at a high clock frequency.SOLUTION: A memory system includes: a memory cell 10 capable of holding data Dout and first signals (switch signals); a holding unit 61 for holding a second signal (VHF) and a third signal (RM); and an output unit for outputting the data. The output unit includes a buffer unit 93 having first, second, and third transistors for outputting the data externally. A frequency includes a first frequency (asynchronous, 66 MHz or 83 MHz) and a second frequency (104 MHz) higher than the first frequency. When the frequency is the second frequency, the first, second, and third transistors can be made into on states, irrespective of values of the first control signals ( , , and ).
摘要翻译：要解决的问题：提供以高时钟频率输出数据的存储器系统。解决方案：存储器系统包括：能够保持数据Dout和第一信号（开关信号）的存储单元10; 用于保持第二信号（VHF）和第三信号（RM）的保持单元61; 以及用于输出数据的输出单元。输出单元包括具有用于从外部输出数据的第一，第二和第三晶体管的缓冲单元93。频率包括比第一频率高的第一频率（异步，66MHz或83MHz）和第二频率（104MHz）。当频率是第二频率时，与第一控制信号（，和）的值无关，可以使第一，第二和第三晶体管成为导通状态。版权所有（C）2012，JPO＆INPIT

15. 发明专利

JP2010009132A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2010009132A
公开(公告)日：2010-01-14
申请号：JP2008164807
申请日：2008-06-24
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： WATANABE TOSHIFUMI , SAITO SAKATOSHI
IPC分类号： G06F21/02 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device, capable of setting an optional protection area while suppressing increase in chip size. SOLUTION: The semiconductor storage device includes a nonvolatile memory having a plurality of blocks each of which is a minimum unit in which data can be independently erased; a volatile memory which serves as a buffer of the nonvolatile memory; a protection SRAM capable of holding protection information for limiting executable operation to each of the blocks; a register capable of reading the protection information corresponding to a block address input from the outside from the protection SRAM and setting it; and a control part which determines, based on the protection information set to the register, whether an operation requested to the block is limited or not. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储装置，能够设置可选的保护区域，同时抑制芯片尺寸的增加。解决方案：半导体存储装置包括具有多个块的非易失性存储器，每个块是可以独立擦除数据的最小单位; 用作非易失性存储器的缓冲器的易失性存储器; 保护SRAM，其能够保持用于限制对每个块的可执行操作的保护信息; 一个能够从保护SRAM读取对应于从外部输入的块地址的保护信息并将其设置的寄存器; 以及控制部，其基于对所述寄存器设置的保护信息，确定对所述块请求的操作是否被限制。版权所有（C）2010，JPO＆INPIT

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