专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JP2009212611A Logic circuit having spin mosfet 有权
标题翻译：具有旋转MOSFET的逻辑电路
公开(公告)号：JP2009212611A
公开(公告)日：2009-09-17
申请号：JP2008051192
申请日：2008-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA HIDEYUKI , ISHIKAWA MIZUE , IGUCHI TOMOAKI , SAITO YOSHIAKI , TANAMOTO TETSUSHI
IPC分类号： H03K19/0944 , H01L21/8238 , H01L27/092 , H01L29/82
摘要： PROBLEM TO BE SOLVED: To provide a logic circuit having a spin MOSFET, for stabilizing long-term operations.
SOLUTION: The logic circuit includes: an n-type or p-type spin MOSFET 4; an input circuit provided with n (n≥2) pieces of input terminals and n pieces of capacitors 6 and 8 respectively provided between the gate of the spin MOSFET and n pieces of the input terminals; a first resistor R
p1 provided between a drive power source and the gate of the spin MOSFET; a p-type MOSFET 10
1 connected serially to the first resistor between the drive power source and the spin MOSFET, for receiving signals obtained by inverting reset signals at the gate; a second resistor R
n1 provided between a ground power source and the gate of the spin MOSFET; and an n-type MOSFET 12
1 connected serially to the second resistor between the ground power source and the gate of the spin MOSFET, for receiving the reset signals at the gate.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有自旋MOSFET的逻辑电路，用于稳定长期操作。解决方案：逻辑电路包括：n型或p型自旋MOSFET 4; 分别设置在自旋MOSFET的栅极和n个输入端之间的n（n≥2）个输入端子和n个电容器6和8的输入电路; 提供在驱动电源和自旋MOSFET的栅极之间的第一电阻器R SB SB1; 在驱动电源和自旋MOSFET之间串联连接到第一电阻器的p型MOSFET 10 <1>，用于接收通过在门处反相复位信号而获得的信号; 设置在地电源和自旋MOSFET的栅极之间的第二电阻器R n1 以及在地电源和自旋MOSFET的栅极之间串联连接到第二电阻器的n型MOSFET 12 ，用于在栅极处接收复位信号。版权所有（C）2009，JPO＆INPIT

12. 发明专利

JP2009171007A Reconfigurable logic circuit 有权
标题翻译：可重新配置的逻辑电路
公开(公告)号：JP2009171007A
公开(公告)日：2009-07-30
申请号：JP2008004192
申请日：2008-01-11
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA HIDEYUKI , ISHIKAWA MIZUE , IGUCHI TOMOAKI , SAITO YOSHIAKI , TANAMOTO TETSUSHI
IPC分类号： H03K19/173 , G11C11/15 , H01L21/82 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L29/82
CPC分类号： H03K19/1733 , G11C11/161 , G11C11/1675 , G11C11/1697
摘要： PROBLEM TO BE SOLVED: To provide a reconfigurable logic circuit which can be integrated highly. SOLUTION: The reconfigurable logic circuit comprises a multiplexer having a plurality of control lines each capable of transmitting individual control data, a plurality of spin MOSFETs where a source and a drain contain magnetic substances and a section for selecting one of the plurality of spin MOSFETs, a circuit for determining whether the magnetization of the magnetic substances in the source and the drain of the spin MOSFET selected by the multiplexer is in a first state or a second state, a first write circuit for feeding a write current to the selected spin MOSFET and bringing the magnetization of the magnetic substance in the selected spin MOSFET into the second state, and a second write circuit for feeding a write current to the spin MOSFET selected by the multiplexer and bringing the magnetization of the magnetic substance in the selected spin MOSFET into the first state. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以高度集成的可重构逻辑电路。解决方案：可重构逻辑电路包括多路复用器，其具有多个控制线，每个控制线能够发送单独的控制数据，多个自旋MOSFET，其中源极和漏极包含磁性物质，以及用于选择多个自旋MOSFET，用于确定由多路复用器选择的自旋MOSFET的源极和漏极中的磁性体的磁化是处于第一状态还是第二状态的电路，用于将写入电流馈送到所选择的第一写入电路自旋MOSFET并使所选择的自旋MOSFET中的磁性物质的磁化进入第二状态，以及第二写入电路，用于将写入电流馈送到由多路复用器选择的自旋MOSFET，并使磁性物质的磁化在所选择的旋转中 MOSFET进入第一状态。版权所有（C）2009，JPO＆INPIT

13. 发明专利

JP2015061043A 抵抗変化メモリ审中-公开
标题翻译：电阻变化记忆
公开(公告)号：JP2015061043A
公开(公告)日：2015-03-30
申请号：JP2013195705
申请日：2013-09-20
申请人：株式会社東芝 , Toshiba Corp
发明人： IGUCHI TOMOAKI , ISHIKAWA MIZUE , SUGIYAMA HIDEYUKI , SAITO YOSHIAKI , TANAMOTO TETSUSHI
IPC分类号： H01L21/8246 , G11C11/15 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/161 , G11C11/15 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/72 , G11C2213/74 , G11C2213/79 , H01L27/224 , H01L27/228 , H01L43/08
摘要：【課題】抵抗変化率が大きな抵抗変化メモリを提供する。【解決手段】本実施形態による抵抗変化メモリは、第1導電型の第1および第2半導体層ならびに前記第1半導体層と前記第2半導体層との間に設けられ前記第1導電型と異なる第2導電型の第3半導体層を備え前記第1半導体層が前記抵抗変化素子に接続された半導体素子と、を有するメモリセルと、前記抵抗変化素子および前記半導体素子に対して、第1読み出し電圧を印加し、前記第1読み出し電圧に続いて前記第1読み出し電圧よりも低い第2読み出し電圧を印加して読み出しを行う読み出し部と、を備えている。【選択図】図1
摘要翻译：要解决的问题：提供具有大电阻变化率的电阻变化存储器。解决方案：电阻变化存储器包括：具有电阻变化元件的存储单元和具有第一导电类型的第一和第二半导体层的半导体元件以及与设置在所述第一半导体层和所述第二半导体层之间的所述第一导电类型不同的第二导电类型的第三半导体层，所述第一半导体层连接到所述电阻变化元件; 以及读出部，向电阻变化元件和半导体元件施加第一读出电压，然后施加比第一读出电压以后的第一读出电压低的第二读出电压，进行读出。

14. 发明专利

JP2014090004A Stacked structure, spin transistor, and reconfigurable logic circuit 有权
标题翻译：堆叠结构，旋转晶体管和可重新配置的逻辑电路
公开(公告)号：JP2014090004A
公开(公告)日：2014-05-15
申请号：JP2012237600
申请日：2012-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： SAITO YOSHIAKI , IGUCHI TOMOAKI , ISHIKAWA MIZUE , SUGIYAMA HIDEYUKI , TANAMOTO TETSUSHI
IPC分类号： H01L29/82 , H01L21/8246 , H01L27/105
CPC分类号： H01L43/10 , H01L29/66984 , H03K19/1733 , H03K19/17728 , H03K19/18
摘要： PROBLEM TO BE SOLVED: To provide a stacked structure including a semiconductor layer, a tunnel barrier layer, and a magnetic layer that have low junction resistance.SOLUTION: A stacked structure includes: a semiconductor layer; a first layer formed on the semiconductor layer, including one element selected from Zr, Ti, and Hf, and having a thickness of one atomic layer or more and five atomic layers or less; a tunnel barrier layer provided on the first layer; and a magnetic layer provided on the tunnel barrier layer.
摘要翻译：要解决的问题：提供包括具有低结电阻的半导体层，隧道势垒层和磁性层的堆叠结构。解决方案：堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，包括选自Zr，Ti和Hf中的一种元素，并且具有一个原子层以上且五原子层以下的厚度; 设置在所述第一层上的隧道势垒层; 以及设置在隧道势垒层上的磁性层。

15. 发明专利

JP2011165258A Nonvolatile memory circuit using spin mos transistor 有权
标题翻译：使用旋转MOS晶体管的非易失性存储器电路
公开(公告)号：JP2011165258A
公开(公告)日：2011-08-25
申请号：JP2010025821
申请日：2010-02-08
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGIYAMA HIDEYUKI , TANAMOTO TETSUSHI , MARUGAME TAKAO , ISHIKAWA MIZUE , IGUCHI TOMOAKI , SAITO YOSHIAKI
IPC分类号： G11C11/15 , H01L21/8244 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/11 , H01L29/82 , H01L43/08
CPC分类号： G11C14/0081
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile memory circuit in order to solve the following problems: in a nonvolatile memory circuit using an MTJ device, data stored in a memory are determined by the resistance values of the MTJ devices when powered, however, when a power supply voltage is low, the resistance of a MOS transistor is very high, and therefore the influence of the resistance value of the MTJ device is very small, and as a result, a malfunction is likely to occur due to variation in resistance value of the MOS transistor when the power supply voltage is low, and therefore high reliability cannot be obtained. SOLUTION: In a memory cell including six transistors (11, 12, 15, 16, 21, and 22), a transistor 12 and a transistor 16 are n-type spin MOS transistors. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了解决以下问题，提供高度可靠的非易失性存储器电路：在使用MTJ器件的非易失性存储器电路中，存储在存储器中的数据由MTJ器件的电阻值确定，然而，当电源电压低时，MOS晶体管的电阻非常高，因此MTJ器件的电阻值的影响非常小，结果是可能发生故障当电源电压低时，MOS晶体管的电阻值的变化，因此不能获得高可靠性。解决方案：在包括六个晶体管（11,12,15,16,21和22）的存储单元中，晶体管12和晶体管16是n型自旋MOS晶体管。版权所有（C）2011，JPO＆INPIT

16. 发明专利

JP2007250754A Designing device and designing method for three-dimensional integrated circuit 审中-公开
标题翻译：三维集成电路的设计和设计方法
公开(公告)号：JP2007250754A
公开(公告)日：2007-09-27
申请号：JP2006071021
申请日：2006-03-15
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAMOTO TETSUSHI , YASUDA SHINICHI , FUJITA SHINOBU
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To design a three-dimensional integrated circuit which is excellent in performance, saving a design cost and a design time.
SOLUTION: The three-dimensional integrated circuit designing device is equipped with a semiconductor circuit forming unit 1, a net list forming unit 2, a two-dimensional layout data forming unit 3, and a three-dimensional layout data forming unit 4. Two-dimensional layout data are divided into two or more layout block data, some of the two-dimensional layout block data are reversed inside out, and each of layout block data is arranged on two or more boards, so that the three-dimensional integrated circuit markedly reduced in two-dimensional area can be formed using the two-dimensional layout data fully.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：设计性能优良，节省设计成本和设计时间的三维集成电路。解决方案：三维集成电路设计装置配备有半导体电路形成单元1，网络列表形成单元2，二维布局数据形成单元3和三维布局数据形成单元4 二维布局数据被分为两个或多个布局块数据，一些二维布局块数据被反向内部，并且每个布局块数据被布置在两个或更多个板上，使得三维布局集成电路在二维区域显着缩小，可以使用二维布局数据充分形成。版权所有（C）2007，JPO＆INPIT

17. 发明专利

JP2007164434A Random number test circuit 有权
标题翻译：随机数测试电路
公开(公告)号：JP2007164434A
公开(公告)日：2007-06-28
申请号：JP2005359236
申请日：2005-12-13
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUMOTO MARI , TANAMOTO TETSUSHI , FUJITA SHINOBU
IPC分类号： G06F7/58
CPC分类号： G06F7/58 , G06F17/15
摘要： PROBLEM TO BE SOLVED: To provide a random number test circuit having no limit on a total number of a random number necessary for test, and preventing increase of a circuit scale even if handling a large number of data necessary for the test to allow miniaturization. SOLUTION: This random number test circuit has: a shift register 1 operating on the basis of a clock, and sequentially storing a serial random number generated from a random number generation element; a comparison circuit 6 comparing values of a first random number outputted from a prescribed stage of the shift register and a second random number apart from the first random number by a predetermined first bit number, generated from the random number generation element; a counter 7 counting generation frequency when the first random number is equal to the second random number to all bits inside the serial random number; and decision circuits 8, 9, 10 deciding that the serial random number is nondefective when a count value of the counter shows the generation frequency within a number predetermined by correlation. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供对测试所需的随机数的总数没有限制的随机数测试电路，并且即使处理测试所需的大量数据，也防止电路规模的增加允许小型化。该随机数测试电路具有：移位寄存器1，其基于时钟操作，并且顺序地存储从随机数生成元件生成的串行随机数; 比较电路6将从移位寄存器的规定级输出的第一随机数与从第一随机数分离的第二随机数与从随机数生成元生成的预定的第一比特数相比较; 当第一随机数等于第二随机数到串行随机数内的所有位时，计数产生频率的计数器7; 以及当计数器的计数值显示通过相关预定的数量内的生成频率时，决定串行随机数是无效的判定电路8,9,10。版权所有（C）2007，JPO＆INPIT

18. 发明专利

JP2005057012A Manufacturing method of electrode 有权
标题翻译：电极制造方法
公开(公告)号：JP2005057012A
公开(公告)日：2005-03-03
申请号：JP2003285347
申请日：2003-08-01
申请人： Toshiba Corp , 株式会社東芝
发明人： TANAMOTO TETSUSHI , SAITO SATOSHI , FUJITA SHINOBU
IPC分类号： B82B3/00 , C01B31/02 , H01J9/02 , H01L21/28 , H01L21/302 , H01L21/44 , H01L21/60 , H01L29/06 , H01L29/41 , H01L29/417 , H01L29/66 , H01L29/786 , H01L35/24
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/025 , H01J9/025 , H01L29/0673 , H01L29/0676 , H01L29/068 , Y10T428/256 , Y10T428/259
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of an electrode, which permits to form an electrode through self-alignment process with respect to the detailed structure of a carbon nanotube, a quantum dot or the like. SOLUTION: The manufacturing method of the electrode comprises a projected part forming step for forming a plurality of projected parts on the surface of a substrate, a first particle introducing step for introducing a first particle whose size is changed by heat, light or a first solvent, between the plurality of projections, a size changing step for changing the size of the first particle by providing the first particle with either one of heat, light or the first solvent, and an electrode material depositing step for depositing the electrode material on the surface of the substrate. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种电极的制造方法，其能够通过自对准工艺形成电极，关于碳纳米管，量子点等的详细结构。解决方案：电极的制造方法包括在基板的表面上形成多个突出部的突出部形成工序，第一粒子导入工序，引入尺寸通过热，光或光改变的第一粒子，在多个突起之间的第一溶剂，用于通过将第一颗粒设置为热，光或第一溶剂中的任一个来改变第一颗粒的尺寸的尺寸改变步骤和用于沉积电极材料的电极材料沉积步骤在基板的表面上。版权所有（C）2005，JPO＆NCIPI

19. 发明专利

JPH11274597A Magnetic reluctance element 失效
标题翻译：磁性元件
公开(公告)号：JPH11274597A
公开(公告)日：1999-10-08
申请号：JP7534498
申请日：1998-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA SHINOBU , INOMATA KOICHIRO , TANAMOTO TETSUSHI
IPC分类号： G11C11/16 , G01R33/09 , G11B5/39 , H01B1/08 , H01B3/00 , H01B3/12 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide an element having magnetic reluctance effect wherein large magnetic reluctance ratio which can be used for a memory element even at room temperature and low magnetic field.
SOLUTION: La
1-x Sr
x MnO
3 (x>0.17) of large Sr composition which becomes ferromagnetic substance and La
1-x Sr
x MnO
3 (x 1-x Sr
x MnO
3 of the same constituent element is used for an insulation film 5, spin scattering of an interface can be restrained and furthermore, a film thickness can be controlled by film formation. Therefore, it is excellent in uniformity of element characteristics unlike the one composed of Fe/Al
2 O
3 . If an insulation film is constructed to be held by ferromagnetic metal and alloy such as La
1-x Sr
x MnO
3 and Fe, CO, Ni, it is easy to use as a memory.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：提供具有磁阻效应的元件，其中即使在室温和低磁场下也可以用于存储元件的大的磁阻比。解决方案：用作隧道绝缘膜3的成为铁磁性物质的大Sr组分的La1-x Srx MnO3（x> 0.17）和成为顺磁性绝缘体的小Sr组分的La1-x Srx MnO3（x <0.17）用于隧道绝缘膜3.由于La1 相同组成元素的-x Srx MnO 3用于绝缘膜5，可以抑制界面的旋转散射，此外，可以通过成膜来控制膜厚度。因此，与由Fe / Al 2 O 3构成的元件特性不同，元件特性的均匀性优异。如果由强磁性金属和La1-x Srx MnO3和Fe，CO，Ni等合金构成绝缘膜，则易于用作记忆体。

20. 发明专利

JP2003258240A RANDOM NUMBER GENERATING ELEMENT 审中-公开
公开(公告)号：JP2003258240A
公开(公告)日：2003-09-12
申请号：JP2002054153
申请日：2002-02-28
申请人： TOSHIBA CORP
发明人： TANAMOTO TETSUSHI , FUJITA SHINOBU
IPC分类号： G06F7/58 , G09C1/00 , H01L29/06 , H01L29/66 , H01L29/788 , H03K3/84
摘要： PROBLEM TO BE SOLVED: To provide a random number generating element having a small scale circuit in which random numbers are generated at an extremely high rate while suppressing inclination. SOLUTION: The random number generating element comprises a pair of first current path 1 and second current path 2 arranged in parallel, and a pair of first micro particle 3 and second micro particle 4 arranged in the vicinity of the first current path 1 and second current path 2 such that charges can move mutually. COPYRIGHT: (C)2003,JPO

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式