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11. 发明专利

JP2010186853A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2010186853A
公开(公告)日：2010-08-26
申请号：JP2009029587
申请日：2009-02-12
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , AOYAMA TOMONORI
IPC分类号： H01L29/78 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/786
CPC分类号： H01L21/28167 , H01L21/02057 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/7624 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66795 , H01L29/785
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method with which a semiconductor device can be manufactured which has a thin gate insulating film of extremely thin effective oxide film thickness in high yield and which has small power consumption.
SOLUTION: The semiconductor device manufacturing method includes: oxidizing a surface of a silicon substrate 1 by using a liquid oxidation agent without exposing the surface to an atmosphere, thereby forming a silicon oxide film 6 on the surface of the silicon substrate 1; forming an aluminum film 7 on the silicon oxide film 6; forming a lanthanum oxide film 8 on the aluminum oxide film 7; forming a hafnium silicate film 9A on the lanthanum oxide film 8; then introducing nitrogen and conducting heat treatment to nitride the hafnium silicate film 9A into a hafnium nitride silicate film 9B, and changing the silicon oxide film 6 to the lanthanum oxide film 8 into lanthanum aluminum silicate through the heat treatment.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种可以制造半导体器件的半导体器件制造方法，该半导体器件具有薄的有效氧化膜厚薄的栅极绝缘膜，并且产生较小的功耗。解决方案：半导体器件制造方法包括：通过使用液体氧化剂氧化硅衬底1的表面而不将表面暴露于大气，从而在硅衬底1的表面上形成氧化硅膜6; 在氧化硅膜6上形成铝膜7; 在氧化铝膜7上形成氧化镧膜8; 在氧化镧膜8上形成硅酸铪膜9A; 然后引入氮气并进行热处理以将硅酸铪膜9A氮化成氮化钇硅酸盐膜9B，并且通过热处理将氧化硅膜6氧化成氧化镧膜8变成硅酸铝镧。版权所有（C）2010，JPO＆INPIT

12. 发明专利

JP2006080372A Method for manufacturing semiconductor device and its manufacturing apparatus 有权
标题翻译：制造半导体器件及其制造装置的方法
公开(公告)号：JP2006080372A
公开(公告)日：2006-03-23
申请号：JP2004264149
申请日：2004-09-10
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , SATO MOTOYUKI , KANEKO AKIO , SEKINE KATSUYUKI , EGUCHI KAZUHIRO
IPC分类号： H01L21/318 , H01L21/31 , H01L21/66 , H01L29/78
CPC分类号： H01L21/02148 , C23C16/401 , C23C16/52 , C23C16/56 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/3143 , H01L21/31604 , H01L21/31612 , H01L21/31645
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device including a MOS transistor which realizes formation of a gate insulating film with less variations in equivalent silicon oxide film thickness and with less characteristic fluctuations, and also to provide an apparatus for manufacturing the semiconductor device.
SOLUTION: The method comprises the steps of depositing the film of an insulative material on the surface of a semiconductor substrate, measuring the thickness of the film or the thickness and composition of the film, setting nitrifying or oxidizing conditions, and nitrifying or oxidizing the film on the basis of the set nitrifying or oxidizing conditions.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决问题的方案：提供一种制造半导体器件的方法，该半导体器件包括MOS晶体管，其实现了形成栅极绝缘膜，其等效氧化硅膜厚度的变化较小并且具有较小的特性波动，并且还提供了一种装置用于制造半导体器件。解决方案：该方法包括以下步骤：将绝缘材料的膜沉积在半导体衬底的表面上，测量膜的厚度或膜的厚度和组成，设定硝化或氧化条件，以及硝化或基于设定的硝化或氧化条件氧化膜。版权所有（C）2006，JPO＆NCIPI

13. 发明专利

JP2005079223A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005079223A
公开(公告)日：2005-03-24
申请号：JP2003305779
申请日：2003-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KANEKO AKIO , SEKINE KATSUYUKI , EGUCHI KAZUHIRO , INUMIYA SEIJI , SATO MOTOYUKI
IPC分类号： C23C14/10 , C23C16/42 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L27/115 , H01L27/1203 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66825 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises a gate insulation film having a high dielectric constant and a gate electrode which contains a dopant and is made of Si or a material containing Si, and which can prevent the generation of fixed electric charge in an interface between the gate insulation film and the gate electrode, and to provide its manufacturing method.
SOLUTION: A gate structure formed on a semiconductor substrate 101 comprises the insulation film 104 having a high dielectric constant, and a reaction prevention layer 105 which is formed on top of the insulation film 104 and composed of a silicon oxide film or a silicon oxide nitride film. The insulation film having a high dielectric constant is formed of a material selected among HfSiO, HfSiON, HfZrSiO, HfZrSiON, ZrSiO, and ZrSiON. By this structure, the fixed electric charge generated when the gate insulation film and a silicon gate electrode 106 are so formed as to be in direct contact with each other can be prevented.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体器件，其包括具有高介电常数的栅极绝缘膜和含有掺杂剂的栅电极，并且由Si或含有Si的材料制成，并且可以防止产生并且在栅绝缘膜和栅电极之间的界面中固定电荷，并提供其制造方法。解决方案：形成在半导体衬底101上的栅极结构包括具有高介电常数的绝缘膜104和形成在绝缘膜104的顶部上并由氧化硅膜或氧化硅氮化物膜。具有高介电常数的绝缘膜由选自HfSiO，HfSiON，HfZrSiO，HfZrSiON，ZrSiO和ZrSiON的材料形成。通过这种结构，可以防止当栅极绝缘膜和硅栅电极106形成为彼此直接接触时产生的固定电荷。版权所有（C）2005，JPO＆NCIPI

14. 发明专利

JP2004259979A Semiconductor device and method for manufacturing it 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004259979A
公开(公告)日：2004-09-16
申请号：JP2003049611
申请日：2003-02-26
申请人： Toshiba Corp , 株式会社東芝
发明人： SEKINE KATSUYUKI , INUMIYA SEIJI , MIZUSHIMA ICHIRO
IPC分类号： H01L27/04 , H01L21/28 , H01L21/318 , H01L21/822 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/495 , H01L29/513 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device comprising an insulating film having a structure capable of thinning a film thickness and including silicon, oxigen, and hydrogen.
SOLUTION: The semiconductor device comprises a silicon substrate 1, and an SiON film 3 provided on the silicon substrate 1 and including silicon, oxygen, nitrogen, and helium having a concentration distribution in a film thickness direction of a maximum concentration of helium on the surface part of the silicon substrate 1 and a maximum concentration of nitrogen on the surface of the opposite side of the silicon substrate 1.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体器件，其包括具有能够使膜厚度薄化并且包括硅，氧原子和氢的结构的绝缘膜。解决方案：半导体器件包括硅衬底1和设置在硅衬底1上并且包括硅，氧，氮和氦的SiON膜3，其具有在最大氦浓度的膜厚度方向上的浓度分布在硅衬底1的表面部分和硅衬底1的相反侧的表面上的氮的最大浓度。版权所有（C）2004，JPO＆NCIPI

15. 发明专利

JP2003204061A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003204061A
公开(公告)日：2003-07-18
申请号：JP2002001546
申请日：2002-01-08
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI , EGUCHI KAZUHIRO , TSUNASHIMA YOSHITAKA
IPC分类号： H01L21/31 , C23C16/30 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/28 , H01L21/316 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/51 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve the characteristics and reliability of a semiconductor device having a silicon oxide film containing a metallic element. SOLUTION: The semiconductor device includes a semiconductor substrate (11), a gate insulating film (14) including the metallic element-containing silicon oxide film, and an electrode (15) formed on the insulating film (14). The metallic element-containing silicon oxide film has a first region near its lower surface, a second region near its upper surface, and a third region between the first and second regions. The concentration distribution of the metallic element contained in the silicon oxide film in the thickness direction has a maximum point in the third region. COPYRIGHT: (C)2003,JPO

16. 发明专利

JP2000243953A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000243953A
公开(公告)日：2000-09-08
申请号：JP4273699
申请日：1999-02-22
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI
IPC分类号： H01L29/78 , H01L21/283
摘要： PROBLEM TO BE SOLVED: To realize high operational speed of an element by suppressing a wiring resistance of a gate electrode. SOLUTION: As shown in (g), immediately after an exposed surface of a silicon substrate 1 at a bottom surface of an opening 9 is made hydrophobic, a Ta2O5 film 11 is deposited to have a thickness of about 5 nm on the substrate surface by a CVD method. In this case, the Ta2O5 film 11 is formed only on the substrate 1 at the bottom surface and not formed on a side wall of the opening 9 or on a silicon oxide film 8. Then as shown in (h), the laminate is subjected to an annealing process in an atmosphere containing, e.g. oxygen activating species of 300 deg.C, to form a 1 nm thick silicon oxide film interfacial layer 13 on the interface between the silicon surface and film 11. Thereafter, a for example, a 10 nm thick titanium nitride film 14 and a 300 nm thick aluminum film 15 are deposited, the entire surface of the laminate is flattened by a CMP method to form a buried gate electrode 16. As a result, a transistor structure is formed as shown in (i).

17. 发明专利

JP2000012795A DESIGNING METHOD OF SEMICONDUCTOR PROCESS AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000012795A
公开(公告)日：2000-01-14
申请号：JP16999498
申请日：1998-06-17
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI , OZAWA YOSHIO , OKUMURA KATSUYA
IPC分类号： H01L21/316 , H01L21/265 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To enable silicon oxide films of different thicknesses to be formed through a method in which the design for process conditions are facilitated. SOLUTION: A sacrificial oxide film 13 of thickness 20 nm is formed on the surface of a silicon board 11, where an element isolation is carried out by an element isolation insulating film 12. Nitrogen ions 15 are selectively implanted into a second region 11a of the silicon board 11, where a thin silicon oxide film is formed. A resist pattern 14 and the sacrificial oxide film 13 are removed. A thermal oxidation process is carried out in a dry atmosphere, whereby a silicon oxide film 161 of thickness 3 nm is formed on the surface of the first region 11a of the silicon board 11, and a silicon oxide film 171 of thickness 6 nm is formed on the surface of a second region 11b of the silicon board 11 where no nitrogen ions are implanted. An additional oxidation process is carried out in an atmosphere that contains water vapor, whereby a silicon oxide film 162 of thickness 5 nm is formed on the first region 11a, and a silicon oxide film 172 of thickness 8 nm is formed on the second region 11b.

18. 发明专利

JPH10173179A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10173179A
公开(公告)日：1998-06-26
申请号：JP33076296
申请日：1996-12-11
申请人： TOSHIBA CORP
发明人： INUMIYA SEIJI , OZAWA YOSHIO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress abnormal oxidation of a metallic film or a metal silicide film of a semiconductor device, by making large the curvature of the lower end portion of its gate electrode in the state of covering with a silicon film and the metal silicide film the exposed surface of the metallic film forming its gate electrode. SOLUTION: Forming a silicon oxide film 202 on a silicon substrate 201, boron ions are implanted into the film 202 to form a first conductive polysilicon film 203. Then, on the film 203, a tungsten silicide film 204 to be the material of a gate electrode is deposited by a sputtering method. Thereafter, forming a resist pattern on the film 204, the tungsten silicide film 204 and the conductive polysilicon film 203 are patterned using the resist pattern as a mask, and the resist pattern is removed therefrom. Subsequently, depositing an amorphous silicon film 206, it is oxidized to form a silicon oxide film 207. In this case, its oxidation is performed at a high temperature not lower than 950 deg.C to make large the radius of curvature of the lower end portion of the gate electrode.

19. 发明专利

JP2010177240A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010177240A
公开(公告)日：2010-08-12
申请号：JP2009015132
申请日：2009-01-27
申请人： Toshiba Corp , 株式会社東芝
发明人： IKENO DAISUKE , AOYAMA TOMONORI , NAKAJIMA KAZUAKI , INUMIYA SEIJI , SHIMIZU TAKASHI , KOBAYASHI TAKUYA
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/08 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/82385 , H01L29/1054 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device providing a low threshold voltage to both an N-type transistor and a P-type transistor; and to provide a method of manufacturing the same.
SOLUTION: The semiconductor device 101 includes an N-type transistor formed in a first region 201 on a substrate, and a P-type transistor formed in a second region 202 on the substrate. The device includes the substrate 111, a first gate insulating film 121 containing silicon, a second gate insulating film 122 containing first metal and oxygen, a third gate insulating film 123 containing second metal different from the first metal and oxygen, a fourth gate insulating film 124 containing hafnium, and a gate electrode layer 131 containing metal and nitrogen. The thickness of the gate electrode layer formed in the second region is set larger than that of the gate electrode layer formed in the first region.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供向N型晶体管和P型晶体管提供低阈值电压的半导体器件; 并提供其制造方法。解决方案：半导体器件101包括形成在衬底上的第一区域201中的N型晶体管和形成在衬底上的第二区域202中的P型晶体管。该器件包括衬底111，包含硅的第一栅极绝缘膜121，包含第一金属和氧的第二栅极绝缘膜122，包含不同于第一金属和氧的第二金属的第三栅极绝缘膜123，第四栅极绝缘膜 124和含有金属和氮的栅电极层131。形成在第二区域中的栅电极层的厚度被设定为大于在第一区域中形成的栅电极层的厚度。版权所有（C）2010，JPO＆INPIT

20. 发明专利

JP2009054609A P-channel mos transistor, n-channel mos transistor, and nonvolatile semiconductor storage device 审中-公开
标题翻译： P沟道MOS晶体管，N沟道MOS晶体管和非易失性半导体存储器件
公开(公告)号：JP2009054609A
公开(公告)日：2009-03-12
申请号：JP2007216906
申请日：2007-08-23
申请人： Toshiba Corp , 株式会社東芝
发明人： INUMIYA SEIJI , KANEKO AKIO , SAITO TOMOHIRO , NAKAJIMA KAZUAKI , AOYAMA TOMONORI
IPC分类号： H01L29/78 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a PMOS transistor using a high-dielectric-constant film for a gate insulating film thereby allowing the power consumption thereof to be reduced.
SOLUTION: The PMOS transistor includes: a semiconductor substrate 1; a P-type impurity diffusion layer 3 formed so as to sandwich a channel region 2 on the surface part of the semiconductor substrate 1; a gate insulating film 4 having insulating films 4a and 4b which are formed on the channel region 2 and contain hafnium or zirconium and a rare-earth element or a group II element, and a silicon oxide film 4c formed on the insulating films 4a and 4b; and a gate electrode 5 formed on the gate insulating film 4.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种使用用于栅极绝缘膜的高介电常数膜的PMOS晶体管，从而允许其功耗降低。解决方案：PMOS晶体管包括：半导体衬底1; 形成为将沟道区域2夹在半导体衬底1的表面部分上的P型杂质扩散层3; 形成在沟道区域2上并含有铪或锆的绝缘膜4a和4b以及稀土元素或II族元素的栅极绝缘膜4和形成在绝缘膜4a和4b上的氧化硅膜4c ; 以及形成在栅极绝缘膜4上的栅电极5.版权所有（C）2009，JPO＆INPIT

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