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11. 发明专利

JP2007171935A Dual display apparatus 有权
标题翻译：双显示设备
公开(公告)号：JP2007171935A
公开(公告)日：2007-07-05
申请号：JP2006297909
申请日：2006-11-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SUNG-MIN , CHU YOUNG-BEE , KIM KYU-SEOK , OH JEONG-SEOK , KIM JEUNG-SOO
IPC分类号： G02F1/1335 , G02F1/13357 , G02F1/1343 , G09F9/40
CPC分类号： G02F1/133555 , G02F1/133615 , G02F2001/133618
摘要： PROBLEM TO BE SOLVED: To provide a dual display apparatus which uses one light unit and one display panel to thereby enable the total thickness of the apparatus to be considerably reduced. SOLUTION: The dual display apparatus includes; the light unit for supplying light; and the display panel which includes a transmissive pixel transmitting the light from the light unit and a reflective pixel reflecting the light from the light unit. The dual display apparatus displays a first image by using the light transmitted through the transmissive pixel from the light unit and displays a second image by using the light reflected by the reflective pixel from the light unit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种双显示装置，其使用一个光单元和一个显示面板，从而能够显着减少装置的总厚度。
解决方案：双显示装置包括：用于提供光的灯单元; 以及显示面板，其包括透射来自光单元的光的透射像素和反射来自光单元的光的反射像素。双显示装置通过使用从光单元透射透射像素的光来显示第一图像，并且通过使用来自光单元的反射像素反射的光来显示第二图像。版权所有（C）2007，JPO＆INPIT

12. 发明专利

JP2007133401A Display panel and display device with the same 审中-公开
标题翻译：显示面板和显示设备
公开(公告)号：JP2007133401A
公开(公告)日：2007-05-31
申请号：JP2006303164
申请日：2006-11-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SUNG-MIN , KIM KYU-SEOK , LEE HO-JUNG
IPC分类号： G02F1/1333 , G02F1/1335 , G02F1/1368 , G09F9/40 , G09G3/20
CPC分类号： G02F1/1333 , G02F2001/133342
摘要： PROBLEM TO BE SOLVED: To provide a display panel that displays each image at both sides, and to provide a display device that is reduced in sizes with the same. SOLUTION: The display panel includes a first display panel, and a second display panel, which is reduced in sizes and oppositely arranged to the first display panel. The first and second display panels are divided into front and rear display areas to display images at both sides. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在两侧显示每个图像的显示面板，并提供一种尺寸减小的显示装置。解决方案：显示面板包括第一显示面板和第二显示面板，其尺寸减小并且与第一显示面板相对布置。第一和第二显示面板分为前后显示区域，以在两侧显示图像。版权所有（C）2007，JPO＆INPIT

13. 发明专利

JP2007039686A Face-bonding tool, face-bonding vacuum device, and adhering method using the same 审中-公开
标题翻译：表面粘合工具，表面粘合真空装置及其使用方法
公开(公告)号：JP2007039686A
公开(公告)日：2007-02-15
申请号：JP2006205263
申请日：2006-07-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KANG HO-MIN , LEE BYOUNG-HUN , BIN KUNKI , HWANG JEONG-HO , KIM SUNG-MIN
IPC分类号： C09J5/00 , C09J5/06 , C09J133/00 , C09J183/04 , G02F1/1333 , G09F9/00
CPC分类号： H01L21/67363
摘要： PROBLEM TO BE SOLVED: To provide a face-bonding tool for adhering an adhesive material to an adherend under a vacuum atmosphere, to provide a face-bonding vacuum device, and an adhering method using the same.
SOLUTION: This face-bonding tool 100 has a fixation part 120 which comprises a plurality of fixation pockets 122, a first frame 110 which comprises movable parts 140 each positioned under the fixation pocket 122 and approachable to or separable from the fixation pocket 122 and first elastic films 150 each positioned under the movable part 140 and elongated or shrunk by a pressure change for moving the movable part 140, and a second frame 160 which comprises second elastic films 170 each separable from or approachable to the first film 110 and elongated or shrunk by the pressure change on a position corresponding to the fixation pocket 122.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在真空气氛下将粘合剂材料粘合到被粘物上的面粘合工具，以提供面粘合真空装置及使用其的粘合方法。解决方案：该面粘合工具100具有固定部分120，该固定部分120包括多个固定凹坑122，第一框架110，其包括每个定位在固定凹槽122下方的可移动部分140，并且可接近或可从固定凹槽 122和第一弹性膜150，每个第一弹性膜150位于可移动部分140的下方并通过用于移动可移动部分140的压力变化而伸长或收缩;以及第二框架160，其包括第二弹性膜170，第二弹性膜170可分离或接近于第一膜110，通过在与固定口袋122相对应的位置处的压力变化而伸长或收缩。（C）2007，JPO＆INPIT

14. 发明专利

JP2006106736A Optical film, backlight assembly having same and display device having same 审中-公开
标题翻译：光学膜，具有相同的背光组件和具有其的显示装置
公开(公告)号：JP2006106736A
公开(公告)日：2006-04-20
申请号：JP2005277578
申请日：2005-09-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： HAN BYUNG-WOONG , KIM KYU-SEOK , CHU YOUNG-BEE , LEE SANG-HEE , KIM JU-HYOUN , KIM SUNG-MIN
IPC分类号： G02B5/02 , F21S2/00 , F21V7/00 , F21V7/22 , F21V8/00 , F21Y101/02 , F21Y103/00 , G02B5/08 , G02F1/1335 , G02F1/13357
CPC分类号： G02B6/0051 , G02B5/02 , G02B6/0041 , G02B6/0055 , G02B6/0063
摘要： PROBLEM TO BE SOLVED: To provide an optical film, a backlight assembly having the same and a display device having the same. SOLUTION: The optical film includes a base layer, a resin layer and a plurality of hollow particles. The resin layer is disposed on a surface of the base layer. The hollow particles are disposed in the resin layer. The base layer is coated with fine hollow particles together with a polyurethane resin. Thus, the thickness of the optical film is made thin and diffusibility and reflectivity of the optical film are improved. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种光学膜，具有该光学膜的背光组件和具有该光学膜的显示装置。光学膜包括基底层，树脂层和多个中空颗粒。树脂层设置在基层的表面上。中空颗粒设置在树脂层中。基层与聚氨酯树脂一起涂覆有细小的中空颗粒。因此，使光学膜的厚度变薄，提高了光学膜的扩散性和反射率。版权所有（C）2006，JPO＆NCIPI

15. 发明专利

JP2013026619A Electric energy generating device and method of driving the same 有权
标题翻译：电力生成装置及其驱动方法
公开(公告)号：JP2013026619A
公开(公告)日：2013-02-04
申请号：JP2012140621
申请日：2012-06-22
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM HYUN JIN , KIM SUNG-MIN , PARK SHOSHIN , SON HYUNG BIN
IPC分类号： H01L41/113 , H01L41/09 , H01L41/187 , H02N1/06 , H02N2/18
CPC分类号： H02N2/18 , H01L41/113
摘要： PROBLEM TO BE SOLVED: To provide an electric energy generating device.SOLUTION: The electric energy generating device includes a piezoelectric structure including a material having piezoelectric characteristics, and an insulating film including a material having electret characteristics. When external energy is supplied to the insulating film, the insulating film contacts the piezoelectric structure and the piezoelectric structure is then deformed to generate electric energy. Also, electric energy is generated when an electrostatic capacitance between the insulating film and a substrate adjacent to the insulating film changes.
摘要翻译：要解决的问题：提供一种电能产生装置。解决方案：电能产生装置包括包括具有压电特性的材料的压电结构和包括具有驻极体特性的材料的绝缘膜。当向绝缘膜供应外部能量时，绝缘膜接触压电结构，然后压电结构变形以产生电能。此外，当绝缘膜和与绝缘膜相邻的衬底之间的静电电容改变时，产生电能。版权所有（C）2013，JPO＆INPIT

16. 发明专利

JP2009060104A Finfet and manufacturing method thereof 有权
标题翻译： FINFET及其制造方法
公开(公告)号：JP2009060104A
公开(公告)日：2009-03-19
申请号：JP2008218400
申请日：2008-08-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SUNG-MIN , KIM MIN-SANG , LEE JI-MYOUNG , KIN DOUIN
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/7856 , H01L29/4925 , H01L29/4958 , H01L29/66795
摘要： PROBLEM TO BE SOLVED: To provide a FinFET and a manufacturing method thereof.
SOLUTION: The pin FET includes: an active fin 102 provided on a substrate 100; a gate oxide film pattern 104 provided on the surface of the active fin 102; a first electrode pattern 106b which is provided on the gate oxide film pattern 104 and extended to cross the active fin 102; a second electrode pattern 108a which is attached on the first electrode pattern 106b, having a line width wider than the first electrode pattern 106b; and a source/drain expansion region 110 provided under the surface of the active fin 102 on both sides of the first electrode pattern 106b. The FinFET like this has an excellent performance, with reduced GIDL current.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种FinFET及其制造方法。引脚FET包括：设置在基板100上的有源鳍片102; 设置在有源鳍片102的表面上的栅极氧化膜图案104; 第一电极图案106b，其设置在栅极氧化膜图案104上并且延伸以跨越有源鳍片102; 第二电极图案108a，其附接在第一电极图案106b上，线宽宽于第一电极图案106b; 以及在第一电极图案106b的两侧设置在有源鳍片102的表面下方的源极/漏极扩展区域110。像这样的FinFET具有出色的性能，减少了GIDL电流。版权所有（C）2009，JPO＆INPIT

17. 发明专利

JP2006079100A Pluggable optical transceiver module assembly 审中-公开
标题翻译：可插拔的光收发器模块组件
公开(公告)号：JP2006079100A
公开(公告)日：2006-03-23
申请号：JP2005263539
申请日：2005-09-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM SUNG-MIN , KWON JIN-WOOK
IPC分类号： G02B6/42 , G02B6/36
CPC分类号： G02B6/4246 , G02B6/4292
摘要： PROBLEM TO BE SOLVED: To provide a pluggable optical transceiver module which can be unplugged from a cage even in a state where an optical fiber connector is inserted, and to provide a pluggable optical transceiver module assembly using the same.
SOLUTION: The pluggable optical transceiver module assembly 100 comprises a bail clip 400 for providing a latching part 428 to be locked by a locking member 525 of the cage 500, and an optical transceiver module 110 with a connector part 200 having a housing part for housing an external connector. The bail clip 400 comprises a main body 410 penetrating through 1st and 2nd ends of the connector part 200, and a lock pin 420 which is supported by the 1st end part of the main body 410 and is made to project or sink in the 2nd end; and a bail 430 which is supported by the 1st end part of the main body 410 at one end and latched on the 1st end of the connector part 200 in a lever shape, and makes the latching part 428 project by use of restoring force of the lock pin 420 by applying force to the other end to sink the latching part 428 and removing the applied force.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在插入光纤连接器的状态下也可以从保持架中拔出的可插拔光收发器模块，并且提供一种使用其的可插拔光收发模块组件。解决方案：可插拔光收发器模块组件100包括用于提供由保持架500的锁定构件525锁定的闩锁部分428的拨号夹子400和具有连接器部件200的光收发器模块110，连接器部件200具有壳体用于容纳外部连接器的部件。吊卡400包括穿过连接器部件200的第一端和第二端的主体410，以及由主体410的第一端部支撑并被制成在第二端部上或底部的锁定销420 ; 以及吊杆430，其一端被主体410的第一端部支撑并且以杠杆形状锁定在连接器部件200的第一端上，并且通过使用闩锁部件428的恢复力而突出锁定销420通过向另一端施加力而使锁定部分428沉降并去除所施加的力。版权所有（C）2006，JPO＆NCIPI

18. 发明专利

JP2005354065A Gate-all-around semiconductor element and method of fabricating the same 有权
标题翻译： GATE全面的半导体元件及其制造方法
公开(公告)号：JP2005354065A
公开(公告)日：2005-12-22
申请号：JP2005167769
申请日：2005-06-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： YUN EUN-JUNG , KIM SUNG-MIN , LEE SUNG-YOUNG
IPC分类号： H01L29/786 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66553 , H01L29/42376 , H01L29/42392 , H01L29/66484 , H01L29/7831
摘要： PROBLEM TO BE SOLVED: To provide a gate-all-around semiconductor element and a method of fabricating the same.
SOLUTION: A pair of pillars that include the source/drain regions is formed by steps of: providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that a portion of the wall remains as a pillar, wherein a sacrificial layer is formed at the bottom of the opening, a channel region is formed to adapt to the sacrificial layer between the pillars, the sacrificial layer is removed, and the gate oxide and gate electrode are formed around the channel region, employing one or more sidewall spacers to define the effective width of the channel region and minimize parasitic capacitance between the source/drain regions and gate electrode.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种全栅半导体元件及其制造方法。解决方案：包括源极/漏极区域的一对支柱由以下步骤形成：提供单晶硅衬底，蚀刻衬底以形成一对间隔开的沟槽，使得单 - 晶体硅位于沟槽之间，用绝缘材料填充沟槽，将杂质注入单晶硅的壁中，并在壁中形成开口，使得壁的一部分保持为柱状，其中形成牺牲层在开口的底部，形成通道区域以适应柱之间的牺牲层，去除牺牲层，并且栅极氧化物和栅电极围绕沟道区形成，采用一个或多个侧壁间隔物来限定沟道区域的有效宽度，并使源极/漏极区域和栅电极之间的寄生电容最小化。版权所有（C）2006，JPO＆NCIPI

19. 发明专利

JP2006352125A METHOD OF MANUFACTURING MOS FIELD EFFECT TRANSISTOR HAVING MULTIPLE CHANNELS, AND MOS FIELD EFFECT TRANSISTOR HAVING MULTIPLE CHANNELS MANUFACTURED BY THE SAME 审中-公开
公开(公告)号：JP2006352125A
公开(公告)日：2006-12-28
申请号：JP2006163490
申请日：2006-06-13
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： SUK SUNG DAE , LEE SUNG-YOUNG , KIN DOIN , KIM SUNG-MIN
IPC分类号： H01L29/786 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a MOS field effect transistor having multiple channels. SOLUTION: A method of manufacturing a MOS field effect transistor having multiple channels comprises: a step of sequentially forming a first material layer 20 and a semiconductor layer 30 that have etching selectivity on a semiconductor substrate 10; a step of forming semiconductor layers 30b having at least a pair of exposed peripheries by means of an etching process using a mask layer, a buried material layer formation process, and a planarization process; a step of forming a gate insulating layer 92a and a gate electrode layer 90 that surround the semiconductor layer 30b having the exposed peripheries; and a step of forming a first ion implantation region 94 by using the gate electrode layer 90 as a mask and forming a second ion implantation region 98 by using an insulating spacer 96 as a mask, thereby obtaining source/drain regions. COPYRIGHT: (C)2007,JPO&INPIT

20. 发明专利

JP2004128508A Mos transistor including multi-channel and its manufacturing method 有权
标题翻译：包括多通道的MOS晶体管及其制造方法
公开(公告)号：JP2004128508A
公开(公告)日：2004-04-22
申请号：JP2003342265
申请日：2003-09-30
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： PARK DONG-GUN , LEE CHANG-SUB , CHOE JEONG-DONG , LEE SHIN-AE , KIM SEONG-HO , KIM SUNG-MIN
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： PROBLEM TO BE SOLVED: To provide a MOS transistor including multi-channel and its manufacturing method. SOLUTION: On a main surface of a semiconductor substrate, an active channel pattern which is equipped with a plurality of channels formed vertically and a plurality of tunnels formed between each of the channels, is formed. Gate electrodes are formed to surround the channels while burying the tunnels on the active channel pattern. Gate insulating films are formed between the gate electrodes and the channels. Source/drain regions are formed on both sides of the active channel pattern to be connected with the channels. A highly integrated transistor in which the horizontal length of the tunnels buried as a gate electrode is limited to the region of gate length and which has a gate length smaller than the channel width, can be attained. COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：提供一种包括多通道的MOS晶体管及其制造方法。解决方案：在半导体衬底的主表面上，形成有垂直形成的多个通道的配置的活性沟道图案，以及形成在各沟道之间的多个通道。形成栅极以围绕通道，同时将隧道埋在有源沟道图案上。在栅电极和通道之间形成栅极绝缘膜。源极/漏极区域形成在与沟道连接的有源沟道图案的两侧。埋入作为栅电极的隧道的水平长度被限制在栅极长度的区域并且栅极长度小于沟道宽度的高度集成的晶体管。版权所有（C）2004，JPO

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