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11. 发明专利

JPH06252865A DIGITAL AUDIO SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH06252865A
公开(公告)日：1994-09-09
申请号：JP3343993
申请日：1993-02-23
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA OSAMU , SEKI KAZUHIKO , KUBOTA SHUJI , KATO SHUZO
IPC分类号： H04B14/06 , H04B14/04 , H04L1/00 , H04Q11/04
摘要： PURPOSE:To provide a digital audio signal processing unit by which deterioration in audio quality due to an error added on a transmission line is surely prevented. CONSTITUTION:A difference comparator signal (k) from an absolute value comparator 7 is set only when an absolute valve of a difference (i) between a received PCM audio signal (a) and a PCM audio signal (h) at one preceding sample exceeds a predetermined threshold level (j), or an overload detector signal (l) from an overload detector 8 is set only when the received PCM audio signal (a) indicates a maximum value expressed in the PCM code consecutively over two samples, or a CRC error detection signal (b) and signal (m) at an output of an OR 9 between the signals (k) and (l) are ANDed by an AND 10 to provide its abnormal sound processing signal (n). The abnormal sound processing signal (n) is given to an output buffer control section 3, which controls a PCM code processing buffer memory 1 and a smoothing filter 2 thereby controlling the abnormal sound elimination processing.

12. 发明专利

JPH0690166A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH0690166A
公开(公告)日：1994-03-29
申请号：JP26556992
申请日：1992-09-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MIZOGUCHI MASATO , SEKI KAZUHIKO , KATO SHUZO
IPC分类号： H03L7/08 , H03L7/10 , H03L7/187
摘要： PURPOSE:To enable high-speed frequency switching without depending on the response time of a phase locked loop. CONSTITUTION:This device is provided with a normal phase difference prediction circuit 8 to detect normal phase difference in the case of oscillation at a fixed frequency from the output value of a phase comparator 1 and to predict the normal phase difference corresponding to a new oscillation frequency from this normal phase difference, and frequency switching control circuit 9. The predictive value of normal phase difference provided from this normal phase prediction circuit 8 at the time of frequency switching is impressed to an adder 6, reference phase generating means composed of a latch 7, and comparative phase generating means 5 composed of a counter 5 by this frequency switching control circuit 9 and held as an initial value. After the control voltage of a voltage controlled oscillator 4 is stablized, the operation of the phase locked loop is started by operating the reference phase generating means and comparative phase generating means 5.

13. 发明专利

JPH0267821A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH0267821A
公开(公告)日：1990-03-07
申请号：JP21858588
申请日：1988-09-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , UMEHIRA MASAHIRO , SAITO SHIGEKI , TARUSAWA YOSHIAKI
IPC分类号： H03L7/187 , H03L7/199
摘要： PURPOSE:To prevent the occurrence of frequency variance at the time of frequency switching to shorten the output switching time by resetting a variable frequency dividing circuit so that the phase difference between the output signal of the variable frequency dividing circuit and a reference signal is about 0 at the time of frequency switching. CONSTITUTION:At the time of frequency switching, a setting circuit 7 sends a loop control signal to open a loop switch 10 and sets frequency division data corresponding to a desired frequency to a variable frequency dividing circuit 2. Simultaneously, the circuit 7 sends a reset signal to the variable frequency dividing circuit 2 with the reference signal as the trigger and sends a loop control signal to close the loop thereafter and equalizes the output signal phase of the variable frequency dividing circuit 2 and the reference signal phase to each other. Consequently, the frequency variance for frequency switching is eliminated. Thus, the output switching time is shortened.

14. 发明专利

JPH01200841A SYSTEM FOR SWITCHING FREQUENCY 失效
公开(公告)号：JPH01200841A
公开(公告)日：1989-08-14
申请号：JP2518788
申请日：1988-02-05
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KAZAMA HIROSHI , SHOMURA TATSURO
IPC分类号： H04J4/00 , H04L5/26
摘要： PURPOSE:To lower a loss probability and to set a communication line with a high using efficiency by switching the oscillation frequency of a frequency variable type frequency oscillation when the number of oscillators which one transmitting and receiving node has is made smaller than the number of frequency divisions of the communication line. CONSTITUTION:Frequency variable type frequency oscillators 11-14 oscillate the signals of arbitrary frequencies by control signals from a frequency control circuit 17, and an oscillator switching circuit 15 selects one of the frequency oscillators 11-14. A frequency converting circuit 16 inputs an IF signal, mixes it with the output signal of the circuit 15, and converts it to an RF signal. By setting the frequencies corresponding to communication channels to the oscillators 11-14 and controlling the circuit 15, the communication line between the transmitting and receiving nodes can be set through the use of all communication channels by the oscillators in the number smaller than the number of the frequency divisions of the communication line. Thus, when the number of oscillators which one transmitting and receiving node has is made smaller than the number of frequency divisions of the communication line, the loss probability can be lowered in comparison with a conventional system, and the communication line can be set with a high line using efficiency.

15. 发明专利

JP2592978B2 失效
公开(公告)号：JP2592978B2
公开(公告)日：1997-03-19
申请号：JP9147790
申请日：1990-04-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KUBOTA SHUJI , MORIKURA MASAHIRO , KATO SHUZO
IPC分类号： H03M13/23 , H03M13/12

16. 发明专利

JPH07273817A DIGITIZED ORTHOGONAL PHASE MODULATION CIRCUIT 失效
公开(公告)号：JPH07273817A
公开(公告)日：1995-10-20
申请号：JP6136694
申请日：1994-03-30
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAKATA TORU , SEKI KAZUHIKO , KUBOTA SHUJI , KATO SHUZO
IPC分类号： H03L7/06 , H04L27/20
摘要： PURPOSE:To unnecessiate a low frequency phase converter by constituting the circuit so that the modulation signal phase-converted by a digital circuit is directly supplied to an image suppression type frequency converter. CONSTITUTION:A selection circuit 103 outputs sine wave signals 156 and 157 as third and fourth cycle signals which are different from orthogonal sine wave signals 155 and 156 in phase by 90 deg., respectively. A second code inversion means periodically inverting the code of one input or output of a multiplier 107 and the code of one input or output of a multiplier 108 is provided on the selection circuit 103 so that the first modulation signal 158 that an adder 106 outputs and the second modulation signal 159 which is different by 90 deg. in the phase of a carrier wave may be obtained in the output of an adder 109, and the circuit is provided with a D/A converter 111 converting the output of the adder 109 into an analog signal. Each output of the D/A converters 110 and 111 is outputted via low-pass filters 112 and 113.

17. 发明专利

JPH01208042A FREQUENCY CONVERSION TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPH01208042A
公开(公告)日：1989-08-22
申请号：JP3237488
申请日：1988-02-15
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KAZAMA HIROSHI , SEKI KAZUHIKO , SHOMURA TATSURO
IPC分类号： H04J4/00
摘要： PURPOSE:To obtain compact constitution suitable for a communication satellite by performing the frequency control of a local oscillator in a period multiplied by integer times the time slot in case of transmitting a signal to a time-divided time slot synchronized with plural frequencies. CONSTITUTION:The oscillation frequency of an oscillator 11 capable of changing the oscillation frequency for plural transmission frequencies is controlled by a control circuit 15. Also, by controlling a buffer circuit 2 by the circuit 15, synchronization with the time slot for communication is taken, and the frequency is changed in the period of the integer times the slot, and transmission is stopped. The oscillator 11 is constituted of a frequency synthesizer and the circuit 15 is operated synchronizing with the output of a synchronous circuit 17 synchronized with the time slot at a program control circuit. By storing arrival information in the circuit 2 during the stoppage of the transmission, the communication can be continued. In such a way, it is possible to miniaturize a local oscillation circuit.

18. 发明专利

JPH07235959A PHASE UNCERTAINTY ELIMINATION CIRCUIT 失效
公开(公告)号：JPH07235959A
公开(公告)日：1995-09-05
申请号：JP4657994
申请日：1994-02-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , KUBOTA SHUJI , KATO SHUZO
IPC分类号： H04L27/22 , H03M13/23 , H04L25/08 , H03M13/12
摘要： PURPOSE:To speed up the phase slip detection of a signal to which convolution-coding and phase modulation are applied in decoding by applying the convolution-coding to a demodulator by a simplified decoder, applying the convolution-coding to it again by a re-encoder, and inverting polarity when those results are compared with a demodulation signal and noncoincidence is obtained. CONSTITUTION:A phase controller 101 performs phase control on the demodulation signal 120, and inputs a signal 122 to the simplified decoder 102 and a delay device A107. Also, the demodulation signal is constituted of an I signal and a Q signal. The controller 101 inverts the polarity of those signals. The same coding as the one applied to a transmission side is applied to a simplified decoding result 123 by the re-encoder 103, and re-coded data 124 is compared with a signal 128 delayed by the delay device A107 by a comparator 104, and a result is inputted to a phase decision circuit 105. The circuit 105 compares a comparison result 125 with an applied phase, and controls the controller 101 by changing a phase control signal 126 when judging that phase change occurs. Decoded data 121 can be obtained by taking the exclusive OR of the decoded result 129 of a viterbi decoder 108 which decodes the comparison result 125 and a signal 130 in which the simplified decoding result 123 is delayed by a delay device 109 by an EXOR 110.

19. 发明专利

JPH06244719A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH06244719A
公开(公告)日：1994-09-02
申请号：JP2945093
申请日：1993-02-18
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , MIZOGUCHI MASATO , KATO SHUZO
IPC分类号： H03L7/18
摘要： PURPOSE:To reduce power consumption, and to attain the high speed of frequency pull-in by sharing a pair of phase synchronizing loops for plural VCO, alternately switching the outputs of the plural VCO, and using it as an output signal. CONSTITUTION:When a selection signal SEL is 'H', a holding circuit 24 holds a control voltage corresponding to a VCO 22, and a holding circuit 25 allows the output of a loop filter 26 to pass as it is. At that time, an output signal OUT is the output of the VCO 22, and a loop back signal LB is the output signal of the VCO 23. Therefore, a phase synchronizing loop is constituted for the output signal of the VCO 23. When the selection signal SEL is 'L', a result opposite to the above mentioned one is obtained, and the phase synchronizing loop is constituted for the output signal of the VCO 22. Therefore, this frequency synthesizer is equipped with only one pair of main circuits such as loop filters, and a VCO control voltage is alternately held, so that the high speed frequency pull-in can be attained, and the power consumption can be reduced.

20. 发明专利

JPH0697929A SYNCHRONOUS WORD DETECTING CIRCUIT 失效
公开(公告)号：JPH0697929A
公开(公告)日：1994-04-08
申请号：JP24368392
申请日：1992-09-11
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SEKI KAZUHIKO , MORIKURA MASAHIRO , KATO SHUZO
IPC分类号： H04L7/10
摘要： PURPOSE:To reduce synchronous word non-detection probability by generating a receiving timing by using a synchronous word detecting position stored in a burst length counter, when the synchronous word of a burst signal is not detected. CONSTITUTION:A burst length counter 33 function as a storage circuit, and when a correlation detector 31 cannot detect synchronization from a burst signal and a correlation detection pulse 105 is not inputted, the pulse separated by burst length is outputted. Based on this synchronous word detecting position, a receiving timing is generated and read-out data 304 is outputted through a read-out control part 32. Accordingly, the receiving burst signal is not destroyed substantially, the probability of the synchronous word non-detection is reduced, and the detection of data loss probability is prevented.

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