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11. 发明专利

JP2006041005A Method and equipment for determining arrangement of semiconductor element forming region, program for determining arrangement of the semiconductor element forming region, and method for manufacturing semiconductor element 审中-公开
标题翻译：用于确定半导体元件形成区域的布置的方法和设备，用于确定半导体元件形成区域的布置的程序，以及制造半导体元件的方法
公开(公告)号：JP2006041005A
公开(公告)日：2006-02-09
申请号：JP2004215364
申请日：2004-07-23
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , HAJI HIROSHI , NAKAGAWA AKIRA , NODA KAZUHIRO , NISHINAKA TERUAKI
IPC分类号： H01L21/027
CPC分类号： G03F7/70433 , H01L21/78
摘要： PROBLEM TO BE SOLVED: To maximize the number of semiconductor elements being acquired per one sheet of semiconductor wafer when arrangement of a plurality of unit element forming regions, i.e. rectangular regions for forming semiconductor elements, is determined in the element formation effective region of the semiconductor wafer. SOLUTION: In the element forming effective region of a semiconductor wafer, a plurality of parallel line section regions are formed, by arranging a plurality of parallel lines at an interval equal to the length of the second line of a unit element forming region, and arranged individually and independently of other parallel line section regions, such that the number of unit semiconductor element forming regions taken out in each parallel line section region is maximized, and the arrangement of respective unit semiconductor element forming regions, in respective parallel line section regions, is determined as the arrangement of the element-forming effective region as a whole. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了在单元形成有效区域中确定多个单位元素形成区域（即用于形成半导体元件的矩形区域）的布置时，使每一片半导体晶片获得的半导体元件的数量最大化的半导体晶片。解决方案：在半导体晶片的形成有效区域的元件中，通过以等于单元元件形成区域的第二线的长度的间隔布置多条平行线来形成多个平行线区域区域并且独立地且独立于其它平行线路区域布置，使得在每个平行线路区域中取出的单位半导体元件形成区域的数量最大化，并且各个单位半导体元件形成区域在各个平行线段部分中的布置区域被确定为整个元件形成有效区域的布置。版权所有（C）2006，JPO＆NCIPI

12. 发明专利

JP2006024633A Plasma processing method and plug formation method 有权
标题翻译：等离子体处理方法及其形成方法
公开(公告)号：JP2006024633A
公开(公告)日：2006-01-26
申请号：JP2004199479
申请日：2004-07-06
申请人： Matsushita Electric Ind Co Ltd , Sharp Corp , シャープ株式会社 , 松下電器産業株式会社
发明人： MARUSAKI TSUNEJI , ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/3065 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a plasma etching method and a plug formation method, with which deposition of a foreign matter to a copper or a failure in shape caused by production of copper sulfide, in plasma etching using sulfur hexafluoride as plasma generation gas on a substrate with copper and silicon present on its front layer.
SOLUTION: In plasma etching for the purpose of forming a plug having the end of a copper electrode embedded in a silicon substrate protruding from the surface of the silicon substrate by removing the surface of the substrate by the plasma etching, a mixture gas mainly containing sulfur hexafluoride is used as the plasma generation gas, and plasma etching is done while the surface temperature of the silicon substrate is kept at 65°C or lower. Thus deposition of the copper sulfide produced during the plasma processing process can be suppressed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供等离子体蚀刻方法和插塞形成方法，在使用六氟化硫作为等离子体的等离子体蚀刻中，通过该等离子体蚀刻方法和插塞形成方法，其中由异硫氰化物生成引起的异物沉积到铜或形状不良在其前层具有铜和硅的衬底上产生气体。解决方案：在等离子体蚀刻中，为了通过等离子体蚀刻去除衬底的表面而形成具有嵌入在硅衬底的表面上突出的硅衬底的铜电极的端部的插头，混合气体主要含有六氟化硫作为等离子体产生气体，并且在将硅衬底的表面温度保持在65℃以下的同时进行等离子体蚀刻。因此，可以抑制在等离子体处理过程中产生的硫化铜的沉积。版权所有（C）2006，JPO＆NCIPI

13. 发明专利

JP2005027963A Portable communication terminal, server, and communication system for healthcare information 审中-公开
标题翻译：便携式通信终端，服务器和通信系统，用于医疗信息
公开(公告)号：JP2005027963A
公开(公告)日：2005-02-03
申请号：JP2003272322
申请日：2003-07-09
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAGAWA AKIRA
IPC分类号： A61B5/00 , A61B5/107 , G06Q10/00 , G06Q50/00 , G06Q50/10 , G06Q50/22 , H04M1/00 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To enable a user to simply and easily obtain health status information available for his/her healthcare with a portable communication terminal without any intentional operations for measuring. SOLUTION: The portable communication terminal 11 includes a skin sensor 15 provided on a surface of an operating part 18 or the like. An information processing part 14 stores skin information of the user detected by the skin sensor 15 during use in a skin information storing part 16, and also transmits the skin information from a transmitting part 19 through a communication network 13 to a server 21. The server 21 stores and accumulates the skin information sent from the portable communication terminal 11 in a skin information storing part 23, generates healthcare information according to the skin information and transmits it to the portable communication terminal 11 in a healthcare information providing part 22. The portable communication terminal 11 displays the received healthcare information on a display part 17, which enables users to obtain adequate healthcare information available for their health management. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了使用户能够使用便携式通信终端简单且容易地获得可用于他/她的医疗保健的健康状况信息，而无需任何有意的测量操作。解决方案：便携式通信终端11包括设置在操作部18等的表面上的皮肤传感器15。信息处理部分14在皮肤信息存储部分16中存储由使用中的皮肤传感器15检测到的用户的皮肤信息，并且通过通信网络13将皮肤信息从发送部分19发送到服务器21。 21在皮肤信息存储部23中存储并累积从便携式通信终端11发送的皮肤信息，根据皮肤信息生成医疗信息，并将其发送到医疗信息提供部22的便携式通信终端11.便携式通信终端11在显示部分17上显示接收到的保健信息，这使得用户能够获得可用于其健康管理的足够的医疗信息。版权所有（C）2005，JPO＆NCIPI

14. 发明专利

JP2008147484A Semiconductor memory, and its manufacturing method 审中-公开
标题翻译：半导体存储器及其制造方法
公开(公告)号：JP2008147484A
公开(公告)日：2008-06-26
申请号：JP2006334191
申请日：2006-12-12
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAGAWA AKIRA
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a bit line contact of a high aspect ratio is attained controlling an increase of the number of manufacturing processes in a DRAM having a CUB structure, and to provide its manufacturing method.
SOLUTION: A bit line contact hole is also opened in a process where a capacitor forming area is opened in a second inter layer insulating film 19, and a conductor buried in the contact hole is used as a contact plug when forming a storage node electrode and a plate electrode later. Thereby, the bit line contact is attained controlling the increase of the number of processes.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储器，其中获得高纵横比的位线接触，从而控制具有CUB结构的DRAM中的制造工艺数量的增加，并提供其制造方法。解决方案：在第二层间绝缘膜19中电容器形成区域打开的过程中，位线接触孔也被打开，并且当形成存储器时，埋入接触孔中的导体被用作接触插塞节点电极和平板电极。由此，可以实现位线接触，从而控制加工次数的增加。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2006295066A Method of manufacturing semiconductor chip, and semiconductor chip 有权
标题翻译：制造半导体芯片的方法和半导体芯片
公开(公告)号：JP2006295066A
公开(公告)日：2006-10-26
申请号：JP2005117221
申请日：2005-04-14
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/3065 , H01L21/301
CPC分类号： H01L21/6835 , H01J2237/334 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/78 , H01L2221/6834 , H01L2221/68354 , H01L2924/30105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip having high flexural strength in a method of manufacturing the semiconductor chip for forming a singulated semiconductor chip by dividing a semiconductor wafer. SOLUTION: In the manufacturing method, plasma etching is applied from a second surface to a semiconductor wafer in which an insulating film is arranged on a divided region on a first surface and a mask for defining the dividing region is arranged on the second surface as a surface opposite to the first surface, thereby removing a portion equivalent to the divided region and exposing the insulating film from the etching bottom surface, and after that, the plasma etching is continuously executed in a state that the exposed insulating film is charged by ions in plasma, thereby removing each of corner portions contacting with the insulating film in each of element forming regions. In this method, anisotropic etching is performed for the semiconductor wafer at one of timings. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过划分半导体晶片来制造用于形成单个半导体芯片的半导体芯片的方法中具有高弯曲强度的半导体芯片。解决方案：在制造方法中，从第二表面向半导体晶片施加等离子体蚀刻，其中绝缘膜布置在第一表面上的分割区域上，并且用于限定分割区域的掩模布置在第二表面上表面作为与第一表面相对的表面，从而去除与分割区域相当的部分并使绝缘膜从蚀刻底表面露出，然后在暴露的绝缘膜被充电的状态下连续执行等离子体蚀刻通过等离子体中的离子，从而去除在每个元件形成区域中与绝缘膜接触的每个角部。在这种方法中，在定时中的一个时刻对半导体晶片进行各向异性蚀刻。版权所有（C）2007，JPO＆INPIT

16. 发明专利

JP2006049403A Method and program for determining arrangement of semiconductor element forming area, and production process of semiconductor element 审中-公开
标题翻译：用于确定半导体元件形成区域的布置方法和程序以及半导体元件的生产过程
公开(公告)号：JP2006049403A
公开(公告)日：2006-02-16
申请号：JP2004225103
申请日：2004-08-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAJI HIROSHI , ARITA KIYOSHI , NAKAGAWA AKIRA , NODA KAZUHIRO
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G03F7/70433 , G03F7/70425
摘要： PROBLEM TO BE SOLVED: To produce a plurality of types of semiconductor element having different profile from one sheet of semiconductor wafer, and to deal with limited production with wide variety flexibly.
SOLUTION: A plurality of areas are formed by sectioning an element formation effective area, a plurality of first unit element formation areas are arranged in a first section area, and a plurality of second unit element formation areas having a profile different from that of the first unit element formation areas are arranged in a second section area. An arrangement where the number of first unit element formation areas being arranged in the first section area independently from other section areas is maximized, and an arrangement where the number of second unit element formation areas being arranged in the second section area independently from other section areas is maximized are determined, respectively, as the arrangements of unit element formation areas in the entire element formation effective area.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了生产具有与一片半导体晶片不同的轮廓的多种类型的半导体元件，并且以灵活的方式处理有限的生产。解决方案：通过对元件形成有效区域进行切片而形成多个区域，多个第一单元元件形成区域布置在第一区域区域中，并且多个第二单元元件形成区域具有与其不同的轮廓。的第一单位元件形成区域布置在第二区域中。其中第一单元元件形成区域的数量与其它区域区域独立地布置在第一区域区域中的布置最大化，并且其中第二单元元件形成区域的数量与第二区域区域中的其它区域区域独立地布置的布置分别确定为整个元件形成有效区域中的单元元件形成区域的布置。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2005057244A Plasma treatment apparatus 有权
标题翻译：等离子体处理装置
公开(公告)号：JP2005057244A
公开(公告)日：2005-03-03
申请号：JP2004149995
申请日：2004-05-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , IWAI TETSUHIRO , NAKAGAWA AKIRA
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/00 , H01L21/683 , H01L21/687 , H01L21/68
CPC分类号： H01J37/32009 , H01J37/32532 , H01J37/32642 , H01L21/67069 , H01L21/67126 , H01L21/6831 , H01L21/68785
摘要： PROBLEM TO BE SOLVED: To provide a plasma treatment apparatus capable of treating multiple kinds of wafers having different sizes at a simple low cost by the same plasma treatment apparatus. SOLUTION: In the plasma treatment apparatus performing an etching treatment at a back side of a circuit formation surface of the wafers, insulating films 26, 27 made of annular ceramics are located on an installation surface 3b of an electrode 3a corresponding to peripheral positions of a large size wafer 6A and a small size wafer 6B. When the wafer 6A is aimed, a ring member 29 is equipped. When the wafer 6B is aimed, there is located a locking member 9 which covers between insulating films 26, 27 on the installation surface 3b and locks an absorption hole 3e, and furthermore, there is equipped a covering member 25 which covers an upper part of the locking member 9. Thereby, the wafers having different sizes can be plasma treated by the same electrode 3a. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够通过相同的等离子体处理装置以简单的低成本处理具有不同尺寸的多种晶片的等离子体处理装置。解决方案：在晶片的电路形成表面的背侧进行蚀刻处理的等离子体处理设备中，由环形陶瓷制成的绝缘膜26,27位于对应于周边的电极3a的安装表面3b上大尺寸晶片6A和小尺寸晶片6B的位置。当晶片6A被瞄准时，配备有环件29。当晶片6B被瞄准时，位于安装表面3b上的绝缘膜26,27之间的锁定构件9，并且锁定吸收孔3e，此外，还设置有覆盖部件25，覆盖部件25覆盖因此，可以通过相同的电极3a对具有不同尺寸的晶片进行等离子体处理。版权所有（C）2005，JPO＆NCIPI

18. 发明专利

JP2004237356A Welding control method and consumable electrode type pulse arc welding equipment 有权
公开(公告)号：JP2004237356A
公开(公告)日：2004-08-26
申请号：JP2003032147
申请日：2003-02-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KAWAMOTO ATSUHIRO , NISHIMURA HITOSHI , NAKAGAWA AKIRA , MASAI TOSHIAKI , SHIMADA AKINAO
IPC分类号： B23K9/09 , B23K9/073 , H02M9/00
摘要： PROBLEM TO BE SOLVED: To provide a welding control method and a consumable electrode type pulse arc welding machine in which spatter generation is suppressed in an unstable arc condition such as at the arc start or during the change of the projection length when a work is positionally deviated.
SOLUTION: The consumable electrode type pulse arc welding machine comprises a current increase setting unit 11 to increase the current value with the elapse of time in a short circuit condition, a current decrease setting unit 12 to prevent increase of the current value as the elapse of time in a short circuit condition, a short circuit current control unit 10 which receives the output of the current increase setting unit 11, the output of the current decrease setting unit 12, and the output of a welding current detection unit 9, and selectively controls and outputs the input from the current decrease setting unit 12 if the welding current immediately before occurrence of short circuit is higher than the preset current value, or selectively controls and outputs the input from the current increase setting unit 11 if the welding current is lower than the preset current value, and an output control unit 14 which receives the output of the short circuit current control unit 10 and the output of an arc short circuit discrimination unit 8, and selectively controls and outputs the output of the short circuit current control unit 10 in the short circuit condition.
COPYRIGHT: (C)2004,JPO&NCIPI

19. 发明专利

JP2007116020A Plasma treating device and plasma treating method 有权
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：JP2007116020A
公开(公告)日：2007-05-10
申请号：JP2005308184
申请日：2005-10-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NAKAGAWA AKIRA , ARITA KIYOSHI , IWAI TETSUHIRO
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To stably and easily separate a plate-like substrate from a substrate placement. SOLUTION: A plasma treating method performs a plasma treatment in a state where the plate-like substrate is held on the placement surface of the substrate placement inside a vacuum chamber. The substrate is held by suction in a lower electrode with suction pressure Pb1 so as to perform the plasma treatment under the condition of treating pressure Pa2. Then, the pressure of a treating space is raised to Pa4 by first in-chamber venting (T7-T8) and, in this state, air blowing is performed from the suction hole of the lower electrode (T10-T11). Thus, the substrate is separated from the lower electrode. Then by the second in-chamber ventilation (T12...), the pressure of the vacuum chamber is raised to the atmospheric pressure. Consequently, the plate-like substrate is stably and easily separated from the substrate placement. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了稳定且容易地将板状基板与基板放置分离。解决方案：等离子体处理方法在将板状基板保持在放置在真空室内的基板的配置面的状态下进行等离子体处理。基板通过抽吸保持在具有吸入压力Pb1的下部电极中，以在处理压力Pa2的条件下进行等离子体处理。然后，通过第一室内排气（T7-T8）将处理空间的压力升高至Pa4，在该状态下，从下部电极（T10-T11）的吸入孔进行吹风。因此，基板与下电极分离。然后通过第二室内通风（T12 ...），将真空室的压力升高至大气压。因此，板状基板稳定且容易地从基板放置分离。版权所有（C）2007，JPO＆INPIT

20. 发明专利

JP2006303077A Method of manufacturing semiconductor chip 有权
标题翻译：制造半导体芯片的方法
公开(公告)号：JP2006303077A
公开(公告)日：2006-11-02
申请号：JP2005120815
申请日：2005-04-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ARITA KIYOSHI , NAKAGAWA AKIRA
IPC分类号： H01L21/301
CPC分类号： H01L21/6835 , H01L21/3065 , H01L21/78 , H01L29/0657 , H01L2221/6834 , H01L2221/68354 , H01L2924/10158 , H01L2924/30105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip of high flexural strength in a method of manufacturing a semiconductor chip for forming separate semiconductor chips by dividing a semiconductor wafer. SOLUTION: In a semiconductor wafer 6 where an insulating film 35 is arranged in a division region R2 of a first surface, a dividing groove R2 is formed to match the division region of a second surface. A plasma etching is performed from the second surface for etching the entire second surface and the surface of dividing groove R2. So, the corner on the second surface is removed while the dividing groove R2 in the division region is removed to make the insulating film 35 exposed from an etching bottom. Plasma etching is continued while electric charges 36 is electrified on the insulating film 35 exposed by the ion in the plasma, to remove a corner 40a on the first surface side contacting the insulating film 35. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过划分半导体晶片制造用于形成分立的半导体芯片的半导体芯片的方法中具有高抗弯强度的半导体芯片。解决方案：在绝缘膜35布置在第一表面的分割区域R2中的半导体晶片6中，形成分割槽R2以匹配第二表面的分割区域。从第二表面进行等离子体蚀刻，以蚀刻整个第二表面和分隔槽R2的表面。因此，除去分割区域中的分割槽R2，使绝缘膜35从蚀刻底部暴露出来，去除第二表面上的拐角。等离子体蚀刻继续，同时电荷36在由等离子体中的离子暴露的绝缘膜35上通电，以去除与绝缘膜35接触的第一表面侧上的角部40a。（C）2007，JPO＆INPIT

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