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11. 发明专利

JP2005159076A Solder packaging method of electronic part 审中-公开
标题翻译：电子部件的焊接包装方法
公开(公告)号：JP2005159076A
公开(公告)日：2005-06-16
申请号：JP2003396885
申请日：2003-11-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HASHIMOTO AKIRA , NIIMI HIDEKI , KASHIWAGI TAKAFUMI , KATSUMATA MASAAKI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a solder packaging method for electronic parts by which a chip or a flip chip can be packaged by printing a solder pattern on the land of a circuit board and high density packaging can be easily attained.
SOLUTION: The solder packaging method consists of a process for packaging a semiconductor flip chip 12 on a circuit board 11, a process for forming a solder pattern 18 on a transfer base material 17, a process for transferring the solder pattern 18 to a solder packaging land 16 on the circuit board 11, a process for sticking and temporarily fixing a semiconductor packaging part such as a chip 20 on the solder pattern 18 transferred to the solder packaging land 16 on the circuit board 11, and a process for heating the circuit board 11 on which the solder packaging part is stuck and temporarily fixed and connecting the solder packaging part to the circuit board 11 by melting solder to a melted state. Consequently, the solder pattern 18 of a narrow pitch can be formed and high density packaging can be attained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种用于电子部件的焊料包装方法，通过其可以通过在电路板的焊盘上印刷焊料图案来封装芯片或倒装芯片，并且可以容易地获得高密度封装。焊料包装方法包括在电路板11上封装半导体倒装芯片12的工艺，在转印基材17上形成焊料图案18的工艺，将焊料图案18转印到电路板11上的焊料包装用焊盘16，将转印到电路基板11上的焊料包装用焊盘16上的焊料图案18上贴附并临时固定芯片20等半导体封装部的工序，以及加热工序焊接包装部分被卡住并临时固定的电路板11，并且通过将焊料熔化成熔融状态将焊料包装部分连接到电路板11。因此，可以形成窄间距的焊料图案18，并且可以实现高密度封装。版权所有（C）2005，JPO＆NCIPI

12. 发明专利

JP2005150446A Method for manufacturing electronic part 审中-公开
标题翻译：制造电子零件的方法
公开(公告)号：JP2005150446A
公开(公告)日：2005-06-09
申请号：JP2003386618
申请日：2003-11-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAGI YUJI , NIIMI HIDEKI , KASHIWAGI TAKAFUMI
IPC分类号： H01L21/60 , H01L21/56
CPC分类号： H01L2224/1134 , H01L2224/73204 , H01L2224/83192
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic part which prevents the adhesion of a semiconductor bare chip and a collet, and reliably delivers resin paste to all areas under the semiconductor bare chip.
SOLUTION: In the method for manufacturing the electronic part, in the electronic part mounting a semiconductor bare chip 7, thermosetting resin paste 1 is coated on the mounting face of a mounting substrate by using a dispenser, and a flat tool 5 is pressed from the surface of the resin paste 1 expanded to all faces of the mounting area of the semiconductor bare chip 7, to mount the semiconductor bare chip 7. The resin paste 1 is spread to all the faces of the mounting area of the semiconductor bare chip 7 prior to the mounting of the semiconductor bare chip 7. Since it is hard for the resin paste 1 already projected to the surrounding of the semiconductor bare chip 7 to receive a thermal affect received from a collet 9, expansion and flowage are not caused, and the resin paste 1 does not infiltrate into the collet 9.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种防止半导体裸芯片和夹头的粘附的电子部件的制造方法，并且可靠地将树脂浆料输送到半导体裸芯片下方的所有区域。解决方案：在制造电子部件的方法中，在安装半导体裸芯片7的电子部件中，通过使用分配器将热固性树脂浆料1涂覆在安装基板的安装面上，平面工具5是从树脂浆料1的表面挤压到半导体裸芯片7的安装区域的所有面上，以安装半导体裸芯片7.树脂膏1扩散到半导体裸片的安装区域的所有面芯片7在安装半导体裸芯片7之前。由于已经投射到半导体裸芯片7的周围的树脂浆料1难以从夹头9接收到热影响，所以不会引起膨胀和流动，并且树脂浆料1不渗透到夹头9中。版权所有（C）2005，JPO＆NCIPI

13. 发明专利

JP2008159844A Electronic component package structure and its method for manufacturing 审中-公开
标题翻译：电子元件包装结构及其制造方法
公开(公告)号：JP2008159844A
公开(公告)日：2008-07-10
申请号：JP2006347133
申请日：2006-12-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KASHIWAGI TAKAFUMI , SUGAYA YASUHIRO , TAKAYAMA RYOICHI , TAKANO ATSUSHI , FURUKAWA MITSUHIRO
IPC分类号： H01L23/02 , H01L23/10
摘要： PROBLEM TO BE SOLVED: To provide a new package structure and its method for manufacturing which simultaneously satisfies both thinning and high reliability of package in an electronic component package composed by forming and sealing a hollow portion on a function element.
SOLUTION: A resin layer in which a space is prepared on a function region and a metal layer are laminated, wherein the metal layer is composed by separating an identical material into a portion forming a lid to cover the space and a portion forming an external terminal, the identical structure can be easily obtained by cutting a whole surface plating to a predetermined thickness after the whole surface plating on the patterned resin layer.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种新的封装结构及其制造方法，其同时满足通过在功能元件上形成和密封中空部分而构成的电子部件封装中的封装的薄型化和高可靠性。解决方案：层叠在功能区域和金属层上制备空间的树脂层，其中金属层通过将相同的材料分离成形成盖以覆盖空间的部分和形成的部分外部端子，在图案化树脂层的整个表面电镀之后，通过将整个表面电镀切割成预定厚度，可以容易地获得相同的结构。版权所有（C）2008，JPO＆INPIT

14. 发明专利

JP2008010694A Substrate for mounting semiconductor, manufacturing method thereof, and mounting structure 审中-公开
标题翻译：用于安装半导体的基板，其制造方法和安装结构
公开(公告)号：JP2008010694A
公开(公告)日：2008-01-17
申请号：JP2006180660
申请日：2006-06-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KASHIWAGI TAKAFUMI , YAGI YUJI , SASAOKA TATSUO
IPC分类号： H01L21/60
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor and a mounting structure therefor which improve the yield of flip chip mounting of a semiconductor component and which can yield high reliability.
SOLUTION: The substrate for mounting semiconductor is provided with a via electrode 8 for interlayer connection in the substrate 3 under an electrode land 4, and a projection 9 is formed on the surface of the electrode land 4 by the via electrode 8. The variety of heights of solder bumps 7 of the semiconductor component 1 is absorbed, mounting with a high yield is available, and, on the other hand, the amount of used solder can be reduced, thereby permitting the prevention of outflow of the solder upon remelting of the same.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于安装半导体的基板及其安装结构，其提高半导体部件的倒装芯片安装的成品率，并且可以产生高可靠性。解决方案：半导体安装用基板在电极焊盘4的下方，在基板3中设置有用于层间连接的通孔电极8，并且通过通孔电极8在电极焊盘4的表面上形成突起9。半导体部件1的焊料凸块7的高度的种类被吸收，高产量的安装是可用的，另一方面，可以减少使用的焊料的量，从而允许防止焊料流出重熔一样。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2006108344A Mask for solder printing and method for forming solder bump 审中-公开
标题翻译：焊接打印掩模和形成焊枪的方法
公开(公告)号：JP2006108344A
公开(公告)日：2006-04-20
申请号：JP2004292221
申请日：2004-10-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NIIMI HIDEKI , KASHIWAGI TAKAFUMI , YAGI YUJI
IPC分类号： H01L21/60 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a method of charging solder paste with small variations and at a short tact time, when the solder paste is charged on a circuit board, in manufacturing an electronic apparatus in which a semiconductor package or circuit components are mounted on the circuit board.
SOLUTION: A film 2 composed of an elastic material having a through hole 4 at the same location as in a through hole 3 is formed on one face of a plate body 1 of a high heat-resistant material having the through hole 3 having a desired shape, and a mask 5 for solder printing is constituted.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种小型变化并且在短时间内对焊膏进行充电的方法，当焊膏充电在电路板上时，在制造其中半导体封装或电路部件安装在电路板上。解决方案：在具有通孔3的高耐热材料的板体1的一个面上形成由弹性材料构成的薄膜2，该弹性材料具有与通孔3相同位置的通孔4 具有期望的形状，并且构成用于焊料印刷的掩模5。版权所有（C）2006，JPO＆NCIPI

16. 发明专利

JP2006093178A Method for manufacturing electronic equipment 审中-公开
标题翻译：制造电子设备的方法
公开(公告)号：JP2006093178A
公开(公告)日：2006-04-06
申请号：JP2004272842
申请日：2004-09-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KASHIWAGI TAKAFUMI , NIIMI HIDEKI , YAGI YUJI
IPC分类号： H05K3/34 , H01L25/00
CPC分类号： H01L2224/73204 , H01L2224/83192 , H01L2924/19105 , Y02P70/613
摘要： PROBLEM TO BE SOLVED: To solve the problem that it is impossible to mount efficiently and in a short time a flip chip mounted semiconductor and a solder mounted component on electronic equipment in a mixed manner and in close vicinity to each other, to propose a new flux applying method and a solder supplying method, and to provide a mounting method suitable for miniaturization of the electronic equipment.
SOLUTION: After a semiconductor chip is flip chip mounted on a circuit board, flux is applied to a component mounting land in one lot. Then, a solder chip structured to hold a plurality of solder pieces on a flux permeable base is placed thereon, and the chip component is placed on the solder chip and is connected to the circuit board by a reflow process.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了解决在混合方式和彼此靠近的情况下，不可能有效地在短时间内安装倒装芯片安装的半导体和焊接安装部件到电子设备上的问题，提出了一种新的助焊剂施加方法和焊料供给方法，并且提供了适合于电子设备的小型化的安装方法。解决方案：在将半导体芯片倒装芯片安装在电路板上之后，一个批次将焊剂施加到部件安装台面上。然后，将构成为将多个焊料保持在焊剂渗透性基体上的焊料片放置在其上，并且将芯片部件放置在焊料芯片上，并通过回流工艺连接到电路板。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2005142411A Method for packaging semiconductor component 审中-公开
标题翻译：包装半导体元件的方法
公开(公告)号：JP2005142411A
公开(公告)日：2005-06-02
申请号：JP2003378269
申请日：2003-11-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NIIMI HIDEKI , KASHIWAGI TAKAFUMI , YAGI YUJI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a method for packaging a semiconductor component which can secure a high reliability by applying resin onto four corners of a region for packaging of the semiconductor component on a circuit substrate.
SOLUTION: A resin film 6b is applied onto a region for mounting the semiconductor component 1 of a circuit substrate 3, and resin paste 6a is applied onto four corners of the region for packaging of the semiconductor component 1 of the circuit substrate 3. Thus, when the resin film 6b and the resin paste 6a are thermally set, the resin paste 6a can be stably filled at the four corners of the region of the semiconductor component 1 between the semiconductor component 1 and the circuit substrate 3 with a high reliability.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种用于封装半导体部件的方法，其可以通过将树脂施加到用于在电路基板上包装半导体部件的区域的四个角上来确保高可靠性。解决方案：将树脂膜6b施加到用于安装电路基板3的半导体部件1的区域上，并且将树脂浆料6a施加到用于封装电路基板3的半导体部件1的区域的四个角上因此，当树脂膜6b和树脂浆料6a被热固化时，树脂浆料6a可以稳定地填充在半导体部件1和电路基板3之间的半导体部件1的区域的四个角处，高度可靠性。版权所有（C）2005，JPO＆NCIPI

18. 发明专利

JP2003273160A Semiconductor mounted module 审中-公开
标题翻译：半导体安装模块
公开(公告)号：JP2003273160A
公开(公告)日：2003-09-26
申请号：JP2002071876
申请日：2002-03-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAGI YUJI , KASHIWAGI TAKAFUMI
IPC分类号： H01L21/60
CPC分类号： H01L2224/0401 , H01L2224/05557 , H01L2224/05571 , H01L2224/05572 , H01L2224/1134 , H01L2224/1601 , H01L2224/16237 , H01L2224/81136 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81385 , H01L2224/81898 , H01L2224/83192 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor mounted module with full of connection reliability without the mounting position deviation of a semiconductor bare chip on a mounting board. SOLUTION: An electrode 12 for connection of the mounting board 10 is formed with a recess 11, and a projected bump 16 of the semiconductor bare chip 14 is guided by the recess 11 and mounted. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供具有连接可靠性的半导体安装模块，而不会使半导体裸芯片在安装板上的安装位置偏差。解决方案：用于连接安装板10的电极12形成有凹部11，并且半导体裸芯片14的突出凸起16由凹部11引导并安装。版权所有（C）2003，JPO

19. 发明专利

JP2006246112A Surface acoustic wave device and its manufacturing method 有权
标题翻译：表面声波装置及其制造方法
公开(公告)号：JP2006246112A
公开(公告)日：2006-09-14
申请号：JP2005060129
申请日：2005-03-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FURUKAWA MITSUHIRO , AZUMA KAZUJI , MAEKAWA YUKIHIRO , KASHIWAGI TAKAFUMI , TAKAYAMA RYOICHI
IPC分类号： H03H9/25 , H03H3/08
CPC分类号： H01L2224/94
摘要： PROBLEM TO BE SOLVED: To solve the problem that a surface acoustic wave device of a conventional CSP type is weak against heat since substrates of different materials are bonded to each other. SOLUTION: The surface acoustic wave device comprises a piezo-electric substrate 11, a comb type electrode 12 provided on the piezo-electric substrate, and a lid object 14 composed of the same quality of the material as the piezo-electric substrate. Even in the case of reducing the device in size and lowering the height of the back of the device, it is made possible to obtain the surface acoustic wave device which is hard to destroy a junction interface with heat, and strong to a temperature change etc. , by using a substrate of the same material, even if it is made of a strong crystal of anisotropy. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了解决由于不同材料的基板彼此结合而导致的常规CSP型的声表面波器件相对于热弱的问题。解决方案：声表面波装置包括压电基板11，设置在压电基板上的梳状电极12和由与压电基板相同质量的盖体14 。即使在使装置尺寸减小并且降低装置的背部的高度的情况下，也可以获得难以破坏接合界面的表面声波装置，并且强到温度变化等通过使用相同材料的基材，即使它是由各向异性的强晶体制成的。版权所有（C）2006，JPO＆NCIPI

20. 发明专利

JP2006245190A Solder bump forming method 审中-公开
标题翻译：焊膏形成方法
公开(公告)号：JP2006245190A
公开(公告)日：2006-09-14
申请号：JP2005057238
申请日：2005-03-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NIIMI HIDEKI , YAGI YUJI , KASHIWAGI TAKAFUMI
IPC分类号： H05K3/34 , B23K1/00 , B23K3/06 , B23K101/42 , H01L21/60 , H05K3/00
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a method for forming solder bump within a short period of time with less number of processes at the time of forming a solder bump on a circuit board, in manufacture of an electronic device where electronic components such as semiconductor element or the like are mounted on a circuit board.
SOLUTION: A protection film 33 and a film 34 are provided on the front surface of the circuit board 31 where an electrode pattern 32 is formed on the surface. An aperture 34a is formed only on the electrode pattern 32 of the circuit board 31 with laser beam 35. The aperture 34a is filled with solder paste 36 and this solder paste is fused and solidified. Thereafter, the solder bump 38 is formed by peeling the film 34 on the circuit board 31.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种用于在电路板上形成焊料凸块时在较短时间内形成焊料凸块的方法，其中在形成焊料凸块时的工艺数量较少，在电子器件的制造中，作为半导体元件等安装在电路板上。解决方案：在电路板31的表面上形成有保护膜33和膜34，其中在表面上形成电极图案32。孔34a仅用激光束35形成在电路板31的电极图案32上。孔34a填充有焊膏36，并且该焊膏被熔化和固化。此后，通过剥离电路板31上的膜34来形成焊料凸点38.版权所有：（C）2006，JPO＆NCIPI

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