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11. 发明专利

JPH04365333A HETERO JUNCTION FIELD EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH04365333A
公开(公告)日：1992-12-17
申请号：JP14165291
申请日：1991-06-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU , INOUE KAORU , IKEDA YOSHITO
IPC分类号： H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To reduce the leakage of a gate by forming SiO2 and an insulating film consisting of a silicon nitride film at the sidewall of a mesa, and forming the lead of a gate on this insulating film. CONSTITUTION:SiO2 is made all over the surface of a substrate, and a silicon nitride film is made thereon. Next, by reactive etching, the silicon nitride film on a mesa is removed, and it is etched into the condition that a thin sin. is left on the mesa and the substrate, and finally the SiO2 left on the mesa is removed by etching, and SiO2 and an insulating film consisting of a silicon nitride film are made on the sidewall of the mesa. Next, a source electrode 14 and a drain electrode 15 are made on an n-type InGaAs cap layer. Next, the n-type InGaAs cap layer is removed, and then a gate electrode 11, a gate lead 12, and a gate pad are made. Hereby, the leakage of the gate can be reduced.

12. 发明专利

JPH03125436A HETERO STRUCTURE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03125436A
公开(公告)日：1991-05-28
申请号：JP26320889
申请日：1989-10-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , JII SHII ARUMAN , MATSUNO TOSHINOBU
IPC分类号： H01L29/201 , H01L21/20 , H01L21/203 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To remarkably lower remaining carrier concentration, to suppress a board leakage current, to facilitate isolation of an element and to improve pinch-off characteristic of a FET by employing an Inx(GayAl1-y)1-xAs four- element mixed crystal buffer layer having a large energy band gap. CONSTITUTION:An InAs composition X of an Inx(GayAl1-y)1-xAs buffer layer 3 is '0' at the side of a GaAs substrate 1, and a value Z substantially lattice- matching to a non-doped InAlAs barrier layer 4 at the layer 4 side, and substantially linearly varied from '0' to the Z. The change rate of the X largely affects influence to the crystallinity of a non-doped InGaAs channel layer 5 of an object, and is necessary to be set to a change rate of 0.15 per 100nm of the thickness of the buffer layer, i.e., 1.5X10 /nm or less. Normally, in the case of Z=0.5, the thickness of the buffer layer of 800nm is used, i.e., -6X10 /nm of change rate is set. On the other hand, the value of Y can be set to an arbitrary value of 0 to 1 since the lattice mismatching of GaAlAs to GaAs is small in the degree to be ignored.

13. 发明专利

JPH02252247A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02252247A
公开(公告)日：1990-10-11
申请号：JP7531089
申请日：1989-03-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU
IPC分类号： H01L29/812 , H01L21/203 , H01L21/338 , H01L29/778
摘要： PURPOSE:To realize high gain by few elements by a method wherein a first FET is formed in a first region containing a first and a second carrier supply layers and channel layers, and a second FET is formed in a second region containing the second carrier supply layer and channel layer. CONSTITUTION:On a semiinsulative GaAs substrate 1, a non-doped GaAs buffer layer 2 is formed: a non-doped AlGaAs buffer layer 3 is grown; thereon, a non-doped GaAs layer 6 is formed. N-type impurity Si is implanted in the region of a double hetero junction FET structure (II), and the layer 6 and the layer 3 are turned into N-type, thereby forming carrier layers 4, 5 on the substrate side of the structure (II). After that, a non-doped AlGaAs spacer layer is formed: a non-doped InGaAs deformation channel layer 8 is grown; a non-doped AlGaAs spacer layer 9 and a surface side N-type AlGaAs carrier supply layer 10 are formed: finally an N-type GaAs cap layer 11 is formed. After the structures (I) and (II) are isolated, each electrode is formed, and an FET is completed.

14. 发明专利

JPH01171175A MAGNETIC STORAGE 失效
公开(公告)号：JPH01171175A
公开(公告)日：1989-07-06
申请号：JP33077287
申请日：1987-12-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU
IPC分类号： G11B23/033
摘要： PURPOSE:To protect stored data from an external magnetic field by obtaining a structure in which a magnetic substance to be a memory medium is included in an armor container. CONSTITUTION:An opening 7 to be opened to the armor container of a part facing to a head is not exposed to an outside due to the protective cover of a sliding system consisting of a metal 5 and a completely diamagnetic superconductor layer 3 formed inside the metal. That is, only when stored information is written and read, the protective cover slides, an opening 6 corresponds to the armor container opening 7, is exposed to the outside, faces to the head, and the device is constituted in such a way. When some magnetic field B is impressed from the outside, since an internal layer 2 of the armor container and an internal layer 3 of the protective cover consist of the completely diamagnetic superconductor which completely shields the magnetic field, due to a Meissner effect, the impressed magnetic field B is prevented by the superconductor layers 3 and 2, it only passes through the resin layer on the external side of the armor container and the metal layer 5 of the protective cover, and does not arrive at a magnetic disk 1 in the armor container. Thus, the data stored in the magnetic disk can be protected from the external magnetic field.

15. 发明专利

JPS6474764A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6474764A
公开(公告)日：1989-03-20
申请号：JP23281487
申请日：1987-09-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU , INOUE KAORU
IPC分类号： H01L21/20 , H01L21/338 , H01L29/205 , H01L29/778 , H01L29/80 , H01L29/812
摘要： PURPOSE:To increase critical film thickness, to reduce a band gap and to augment the difference (DELTAEc) of conduction bands by forming a grated channel layer, in which the composition ratio of a multicomponent mixed-crystal semiconductor is selected so that lattice matching can be conducted sufficiently with the layer of a substrate on the interface between a channel layer and the layer on the substrate side and changed continuously toward the surface side. CONSTITUTION:A undoped GaAs buffer layer 2 and a grated InxGa1-xAs layer 3 are shaped onto a semi-insulating GaAs substrate 1. Lattice matching is performed completely as x=0, the same GaAs as the layer 2, on the interface with the GaAs buffer layer 2 in the variation of a composition ratio (x), (x) is increased toward the surface of the substrate, and a band gap is maximized as x=1, InAs, on the surface side from the center of a channel, DELTAEc is also maximized and mobility is also maximized. (x) is gradually reduced again toward the surface side, and lattice matching is executed as x=0, GaAs, on the interface with an undoped AlxGa1-xAs layer (x=0.3) 4.

16. 发明专利

JP2005011876A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005011876A
公开(公告)日：2005-01-13
申请号：JP2003171932
申请日：2003-06-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIROSE YUTAKA , IKEDA YOSHITO , MATSUNO TOSHINOBU
IPC分类号： H01L21/28 , H01L21/338 , H01L29/812 , H01L33/32 , H01L33/40 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To reduce contact resistance and parasitic resistance of a semiconductor device. SOLUTION: An ohmic contact forming region 13 is irradiated with electron beams 15 from above a gallium nitride (GaN) semiconductor layer 12 formed on base metal substrate sapphire 11. In a region irradiated with the electron beams 15, chemical bond of Ga and N is cut by high energy of the electron beams and thermal energy of current. An electron beam inducing defect region 16 formed of a crystal defect and residual Ga is generated in GaN crystal with an N hole as a center. In the defect region 16, the N hole operates as an impurity level contributed to electron supply. Concentration of the electrons in the contact forming region 13 is raised, and residual Ga shows a metallic feature. Thus, resistance in the contact forming region 13 is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：降低半导体器件的接触电阻和寄生电阻。解决方案：欧姆接触形成区域13由形成在基底金属衬底蓝宝石11上的氮化镓（GaN）半导体层12的上面用电子束15照射。在用电子束15照射的区域中，Ga的化学键并且N被电子束的高能量和电流的热能切断。在以N孔为中心的GaN晶体中产生由晶体缺陷和残留Ga形成的电子束诱导缺陷区域16。在缺陷区域16中，N孔作为有助于电子供给的杂质水平。接触形成区域13中的电子浓度升高，剩余的Ga显示出金属特征。因此，接触形成区域13中的电阻降低。版权所有（C）2005，JPO＆NCIPI

17. 发明专利

JP2001267555A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001267555A
公开(公告)日：2001-09-28
申请号：JP2000080242
申请日：2000-03-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHII KATSUNORI , INOUE KAORU , MATSUNO TOSHINOBU , IKEDA YOSHITO , MASATO HIROYUKI
IPC分类号： H01L29/73 , H01L21/306 , H01L21/316 , H01L21/331 , H01L21/335 , H01L21/338 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/812 , H01S5/028 , H01S5/323
摘要： PROBLEM TO BE SOLVED: To enable forming an insulating film which is superior in adhesivity with group III nitride semiconductor and electrical or optical characteristics. SOLUTION: This semiconductor device is provided with an active region 12A, composed of GaN based semiconductor grown on a substrate 11 composed of Si, and an insulating oxide film 12B which is formed through oxidation of the GaN based semiconductor and arranged around the active region 12A. On the active region 12A, a gate electrode 13, which makes Schottky-contact with the active region 12A and formed so as to stretch on the insulating oxide film 12A and has a lead-out part 13a on the insulating oxide film 12B, and ohmic electrodes 14, which have intervals from both side portions in a gate longitudinal side of the gate electrode 13, are turned into a source electrode and a drain electrode.

18. 发明专利

JPH11150129A SEMICONDUCTOR DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH11150129A
公开(公告)日：1999-06-02
申请号：JP23248198
申请日：1998-08-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ANDA YOSHIHARU , MATSUNO TOSHINOBU , YANAGIHARA MANABU , TANABE MITSURU , MATSUI TOSHIAKI , HIROSE NOBUMITSU
IPC分类号： G03F7/26 , H01L21/027 , H01L21/338 , H01L29/41 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To obtain a good forward taper at the leg of a gate electrode such that the diameter is increased at the top side part, while high throughput and high stability are attained when a T-type gate electrode having a top part and a leg part extending downward therefrom is formed. SOLUTION: A resist film 35 with about 200 nm thickness of PMMA (polymethyl methoacrylate) for EB(electron beam) exposure is applied on a substrate 21, and an upper layer resist film 36 for i-line exposure is applied onto the lower layer resist film 35. A mixing layer 37 of both resist films is then formed on the interface between the upper and lower resist films 36, 35, The upper layer resist film 36 is then developed by the i-line exposure, except for the region 36a for forming the top part to obtain an upper layer opening 36b. Furthermore, the mixing layer 37 and the leg part forming region 35a of the layer resist film 35 are developed through EB exposure to obtain a lower opening 35b having a forward taper.

19. 发明专利

JPH08321518A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08321518A
公开(公告)日：1996-12-03
申请号：JP21228995
申请日：1995-08-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： FUJIMOTO HIROMASA , UDA TOMOYA , OTA TOSHIMICHI , MASATO HIROYUKI , MATSUNO TOSHINOBU
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE: To provide a manufacturing method which can form a power GaAs MESFET of high performance, with excellent yield while keeping a high gate- drain withstand voltage. CONSTITUTION: An N-type active layer 12, an N type source region 14 and a drain region 15 are formed in specified regions on a GaAs substrate 10. After a silicon oxide film 16 and a silicon nitride film 17 are deposited, a source electrode 19 and a drain electrode 20 are formed. Over-etching is performed for the silicon nitride film 17 by using a resist mask 21 formed on the silicon nitride film 17. Hence the upper layer part of the silicon oxide film 16 in a gate electrode forming region is eliminated, and the carrier concentration just under a gate electrode in the active layer 12 is reduced. Thereby the withstand voltage between the gate and the drain is improved. After the lower later part of the silicon oxide film 16 in the gate electrode forming region is eliminated, a gate electrode is formed in the eliminated part.

20. 发明专利

JP2530496B2 失效
公开(公告)号：JP2530496B2
公开(公告)日：1996-09-04
申请号：JP18057489
申请日：1989-07-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOE KAORU , JEI SHII ARUMAN , MATSUNO TOSHINOBU
IPC分类号： H01L29/205 , H01L21/203 , H01L21/337 , H01L21/338 , H01L29/778 , H01L29/808 , H01L29/812

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