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1. 发明专利

JP2007024800A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007024800A
公开(公告)日：2007-02-01
申请号：JP2005210717
申请日：2005-07-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YOSHIDA SHINJI , IKEDA YOSHITO , YAMAGUCHI TAKUMI , MURATA TAKAHIKO , KASUGA SHIGETAKA
IPC分类号： G01J1/02 , H01L21/3065 , H01L27/14 , H01L31/00
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having a hollow structure, that improves the yield by preventing damages to membranes. SOLUTION: When manufacturing the semiconductor device, having the hollow structure by etching of sacrificial layer, a vent hole for ventilating etching gas is formed in the sacrificial layer, and with the sacrificial layer left in a hollow part, a dicing process of a wafer, a dice bond process and a wire bond process are executed, and then the sacrificial layer is removed by etching. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供具有中空结构的半导体器件的制造方法，其通过防止对膜的损害来提高产率。解决方案：当通过蚀刻牺牲层制造具有中空结构的半导体器件时，在牺牲层中形成用于通风蚀刻气体的通气孔，并且牺牲层留在中空部分中，切割工艺执行晶片，晶片接合工艺和引线键合工艺，然后通过蚀刻去除牺牲层。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005260172A Manufacturing methods of semiconductor device and semiconductor laser equipment 有权
标题翻译：半导体器件和半导体激光器件的制造方法
公开(公告)号：JP2005260172A
公开(公告)日：2005-09-22
申请号：JP2004073148
申请日：2004-03-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KANDA ATSUHIKO , IKEDA YOSHITO , HIROSE YUTAKA
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/324 , H01L21/331 , H01L21/338 , H01L29/737 , H01L29/78 , H01L29/786 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide manufacturing methods, capable of easily obtaining a semiconductor device and semiconductor laser equipment which does not have residual damages to semiconductor layer by etching and are superior in the high-frequency characteristics and in high power characteristics. SOLUTION: A gate recess 5a is formed, by laminating a semiconductor layer 11 consisting of a III-V group nitride semiconductor on a substrate 1 and by etching the semiconductor layer 11. After that, etching damages generated in the semiconductor layer 11 is made to recover, in such a way that a silicon film 6 is deposited on the semiconductor layer 11, and that the semiconductor layer 11 is treated in heat with the silicon film 6. A III-V group nitride electron device improved in the high-frequency characteristics and in the high power characteristics can be manufactured. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够容易地获得半导体器件和半导体激光设备的制造方法，该半导体器件和半导体激光设备通过蚀刻对半导体层没有残余损伤，并且在高频特性和高功率特性方面是优异的。解决方案：通过在基板1上层叠由III-V族氮化物半导体构成的半导体层11和蚀刻半导体层11，形成栅极凹部5a。之后，在半导体层11中产生的蚀刻损伤以使硅膜6沉积在半导体层11上，半导体层11与硅膜6进行加热处理的方式进行恢复。III-V族氮化物电子器件的高度提高可以制造频率特性和高功率特性。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004056146A Method for manufacturing semiconductor device 有权
公开(公告)号：JP2004056146A
公开(公告)日：2004-02-19
申请号：JP2003275858
申请日：2003-07-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： INOUE KAORU , IKEDA YOSHITO , NISHII KATSUNORI , HIROSE YUTAKA
IPC分类号： H01L21/76 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device consisting of a group III-V nitride semiconductor in whose manufacturing process an element-separating and insulating film is formed in a short time and silicon is diffused in a process for forming the element-separating and insulating film without causing damage to electric characteristics, and those processes can be carried out together.
SOLUTION: A GaN layer 33 and an AlGa layer 37 are formed on a substrate 31, and an oxidized protective film 38 made of silicon is selectively formed on the AlGaN layer 37. Then, the product is loaded in an oxidizing atmosphere at about 1,000°C and is heat-treated about for 1-2 hours. At this time, in the region not covered with the oxidized protective film 38, the GaN layer 33 and the AlGaN layer 37 are oxidized from the surface inside, and the element seperately insulating film 39 made of the oxides of the AlGaN and GaN are formed. Moreover, an AlGaN layer 36A containing added silicon is formed on the AlGaN layer 37 by the heat treatment.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2001274140A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001274140A
公开(公告)日：2001-10-05
申请号：JP2000084336
申请日：2000-03-24
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： INOUE KAORU , NISHII KATSUNORI , IKEDA YOSHITO , MASATO HIROYUKI
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/47 , H01L29/812 , H01L29/872 , H01S5/323
摘要： PROBLEM TO BE SOLVED: To enhance adhesion of an insulating film formed on a GaN-based semiconductor, while reducing the contact resistance of an ohmic electrode. SOLUTION: The surface of a GaN-based semiconductor layer 2 is reformed or cleaned by plasma etching the surface of the GaN-based semiconductor layer 2, using a gas containing ammonia.

5. 发明专利

JP2000012490A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000012490A
公开(公告)日：2000-01-14
申请号：JP17241198
申请日：1998-06-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MASATO HIROYUKI , IKEDA YOSHITO
IPC分类号： H01L21/301 , H01L21/338 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device with high yield while protecting a semiconductor substrate against crack and warp. SOLUTION: A plurality of semiconductor elements 5 are formed on a semiconductor substrate 1 secured such that the surface arranged with the semiconductor elements 5 faces a supporting substrate 6. The semiconductor substrate 1 is divided for each semiconductor element 5 and the supporting substrate 6 is bonded to an expanding/contracting sheet 10. The supporting substrate 6 is divided for each semiconductor element 5 and separated from the expanding/contracting sheet 10 along with the semiconductor element 5. The semiconductor substrate 1 is formed on a package 11 and then the supporting substrate 6 is separated therefrom.

6. 发明专利

JPH09275164A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH09275164A
公开(公告)日：1997-10-21
申请号：JP28079096
申请日：1996-10-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKAI HIROYUKI , IKEDA YOSHITO , NISHII KATSUNORI , INOUE KAORU , YOSHIDA TAKAYUKI
IPC分类号： H01L23/12 , H01L23/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device high in reliability and low in an insertion loss using a thick film BCB film as a dielectric film. SOLUTION: On a substrate 501, there are sequentially formed a ground conductive film 502; an insulation thin film 503 and a BCB film 504. On the BCB film 504, a wiring conductive film 506 is formed, and a part of the wiring conductive film 506 is connected in a flip-flop manner to a semiconductor chip 511. That is, a signal wire 512 of the semiconductor chip 511 is connected via a bump 513. As MFIC using the BCB film 504 as a dielectric film forms the ground insulation thin film 503 of the BCB film 504, a close adhesion of the BCB film 504 to the ground is improved, an isolation of the BCB film 504 can be prevented and a semiconductor device high in reliability can be realized.

7. 发明专利

JPH04365333A HETERO JUNCTION FIELD EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH04365333A
公开(公告)日：1992-12-17
申请号：JP14165291
申请日：1991-06-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MATSUNO TOSHINOBU , INOUE KAORU , IKEDA YOSHITO
IPC分类号： H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To reduce the leakage of a gate by forming SiO2 and an insulating film consisting of a silicon nitride film at the sidewall of a mesa, and forming the lead of a gate on this insulating film. CONSTITUTION:SiO2 is made all over the surface of a substrate, and a silicon nitride film is made thereon. Next, by reactive etching, the silicon nitride film on a mesa is removed, and it is etched into the condition that a thin sin. is left on the mesa and the substrate, and finally the SiO2 left on the mesa is removed by etching, and SiO2 and an insulating film consisting of a silicon nitride film are made on the sidewall of the mesa. Next, a source electrode 14 and a drain electrode 15 are made on an n-type InGaAs cap layer. Next, the n-type InGaAs cap layer is removed, and then a gate electrode 11, a gate lead 12, and a gate pad are made. Hereby, the leakage of the gate can be reduced.

8. 发明专利

JPH04206842A FORMATION OF PAD 失效
公开(公告)号：JPH04206842A
公开(公告)日：1992-07-28
申请号：JP33810890
申请日：1990-11-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHII KATSUNORI , IKEDA YOSHITO , AZUMA CHINATSU
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent the thickness of Au of a pad from decreasing, and keep the pad surface clean without roughing and denaturing, when a thin film existing on a substrate except a pad part is eliminated, by forming an insulating film or a metal film on the upper surface of Au turning to a pad. CONSTITUTION:An Au thin film 13 is formed. A desired photo resist pattern 14 is formed on the film 13 by a punched-out pattern. In the pattern 14, Au is selectively formed by plating, and an Au-plated pattern 15 is formed. On the whole surface, Ti, e.g. is formed to be 700Angstrom thick as a second metal film 16 by evaporation. By a lift-off method, the second metal film 16 is formed only on the Au-plated pattern 15. The Au thin film 13 except the Au-plated pattern 15 is eliminated by wet etching. First metal 12 and the second metal 16 are eliminated at the same time. After that, on the whole surface, a silicon nitride film, e.g. is formed to be 8000Angstrom thick, as an insulating film 17 turning to a protective film. A desired aperture part 18 is formed on an Au-plated pattern 15.

9. 发明专利

JPH03241749A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03241749A
公开(公告)日：1991-10-28
申请号：JP3863490
申请日：1990-02-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHII KATSUNORI , IKEDA YOSHITO , AZUMA CHINATSU
IPC分类号： H01L29/812 , H01L21/338 , H01L29/417
摘要： PURPOSE:To prevent the transverse diffusion of a gate metal in a gate interface by leaving an insulating film in the sidewall of a gate electrode-forming opening. CONSTITUTION:A first gate metal 6 is formed on the whole surface by a normal deposition according to EB deposition so that a part becoming a gate metal 8 is left in an etched part 5. Then, a second insulating film 7 is formed on the whole surface by plasma CVD method and the whole surface is subjected to reactive etching so that the first gate metal 6 of a gate opening bottom is exposed while the second insulating film 7 of a gate opening sidewall is left as it is. Subsequently, the second gate metal 8 is formed on the whole surface by deposition and the first gate metal 6 and the second gate metal 8 are etched by a gate electrode pattern larger than a gate electrode opening 4 to form a T-shaped gate electrode 9. Thus, it is possible to prevent the transverse diffusion of the gate metal to a recess interface.

10. 发明专利

JPH0340438A MANUFACTURE OF FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH0340438A
公开(公告)日：1991-02-21
申请号：JP17411689
申请日：1989-07-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SATO JUNKO , IKEDA YOSHITO
IPC分类号： H01L21/265 , H01L21/338 , H01L29/812
摘要： PURPOSE:To contrive the stable manufacture of a field-effect transistor by a method wherein a gate length is controlled by the thickness of a second insulating film using a multiple deposition method. CONSTITUTION:A first insulating film 3 is applied on a semi-insulative GaAs substrate 2 with an N-type layer 1 formed in it by ion implantation and a window is opened in the photoresist. Then, a second insulating film 4 dissimilar to the film 3 is deposited by a multiple deposition method in such a way as to cover the opening part. The film 4 is etched by an RIE method to provide an opening part on the layer 1. A metal layer 5 formed by normal deposition of a high-melting point metal is formed, the surface of the layer 5 is flattened by a resist 6 and the layer 5 is etched using the resist 6 as a mask and is used as a gate electrode 7. The film 3 is removed by a wet etching method and an ion implantation is performed using the electrode 7 and the film 4 as masks to form n layers 8 which are impurity regions. Then, the film 4 is removed by wet etching and an ion-implantation is performed using the electrode 7 as a mask to form n' layers 9, which are thinner than the layers 8 and have an impurity concentration stronger than that of the layer 1. Lastly, the whose surface is covered with an insulating film 10 and an annealing is performed to activate. By such a way, an LDD structure can stably be formed.

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