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11. 发明专利

JP2000298643A DATA PROCESSOR 失效
公开(公告)号：JP2000298643A
公开(公告)日：2000-10-24
申请号：JP10563999
申请日：1999-04-13
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KATSURAGI MASAHIKO
IPC分类号： G06F13/36 , G06F5/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To facilitate the design of a peripheral device interface control circuit connected to a CPU bus. SOLUTION: Peripheral device interface circuits 120 to 123 connected to a CPU bus 103 consist of core parts 130 to 133 and variable interface blocks 140 to 143. The blocks 140 to 143 consist of a parameter register setting plural parameters corresponding to plural bus specifications that can be held by the bus 103 and an interface circuit performing an operation made to meet the specifications of the bus 103. A peripheral device interface control circuit having the same circuit structure can be used even though bus specifications requested by a CPU 102 are changed.

12. 发明专利

JPH08340495A SPLIT SCREEN DISPLAY SYSTEM 失效
公开(公告)号：JPH08340495A
公开(公告)日：1996-12-24
申请号：JP14446595
申请日：1995-06-12
申请人： HITACHI LTD
发明人： OKUMA KATSUMI , SHIMURA TAKANORI , KATO JUNICHI
IPC分类号： H04N5/45 , H04N7/14
摘要： PURPOSE: To display a new screen such as a self-portrait, etc., without impeding displays of respective images displayed in respective split screens by overwriting and displaying new screens smaller in size than each split screen on dividing lines. CONSTITUTION: A main image display control part 22 detects the dividing lines of the respective split screens and a screen control part (image reduction part 20 and self-portrait display control part 23) overwrite and display the new screen of size smaller than the respective split screens on the dividing lines. Namely, on the dividing lines of the respective split screens or on intersections of the respective split screens when the number of the split screens is three, the new screen is overwritten preferentially to display the self-portrait, etc. In this case, the displays of the respective images in the respective split screens are not impeded. If there is an unused split screen, the new screen is overwritten preferentially in the blank split screen. Further, a new screen is allocated to the entire surface of the display, and the respective split screens are reduced and allocated to positions where the image in the new screen is readable without trouble.

13. 发明专利

JPH07193202A GATE ARRAY 失效
公开(公告)号：JPH07193202A
公开(公告)日：1995-07-28
申请号：JP33051093
申请日：1993-12-27
申请人： HITACHI LTD
发明人： HATANO YUJI , KIKUCHI TAKAFUMI , HOTTA MASAO , SHIMURA TAKANORI , SHIRAISHI YOICHI , AKAZAWA TAKASHI , HIRAKI MITSURU , KIUCHI ATSUSHI
IPC分类号： H01L27/118 , H01L21/82 , H01L27/10
摘要： PURPOSE:To define the final function in an interconnection layer step after forming a chip divided at a region where a gate pattern suited to realize functions in the least areas every function block is regularly lengthwise and crosswise formed. CONSTITUTION:A base chip 101 is divided into a random logic block 111, data puss block 112, ROM block 113 and RAM block 114, each having a block- inherent gate pattern regularly arranged lengthwise and crosswise. The chip completes logic functions by adding interconnection layers. The blocks 111, 112, 113 and 114 are composed of a random logic gate pattern 121, data path gate pattern 122, data gate pattern 123 and RAM gate pattern 124, respectively.

14. 发明专利

JPH06326692A DECODER FOR ERROR CORRECTION CODE 失效
公开(公告)号：JPH06326692A
公开(公告)日：1994-11-25
申请号：JP11274293
申请日：1993-05-14
申请人： HITACHI LTD
发明人： OKUMA KATSUMI , TAKIZAWA MASAAKI , SHIMURA TAKANORI
IPC分类号： H03M13/00 , H04L1/00 , H04L7/00 , H04L7/08
摘要： PURPOSE:To detect a synchronous position at a high speed while reducing the scale of an entire device by utilizing a FIFO memory for inputting information data after error correction and detecting synchronization as a data buffer for recording synchronous pattern judged results before synchronization is established and in the case of step-out of synchronization. CONSTITUTION:When the step-out of a frame synchronization is detected by a frame synchronization monitoring part 31 or when it is required to obtain frame synchronization such as immediately after the reset of a circuit or the like, an error correction control part 35 sends signals for indicating to the effect that the detection of the frame synchronization is performed to a frame synchronization detection part 34, the frame synchronization monitoring part 31 and an error correction circuit 32. Also, the signals for indicating to the effect that the frame synchronization is being detected are sent to a code memory 33 as well and the frame synchronization detection part 34 uses the code memory 33 as a memory for detecting the frame synchronization. While the synchronization is detected, the error correction circuit 32 does not correct errors and does not write data to the code memory 33.

15. 发明专利

JPH04315217A CD-ROM LIBRARY CONTROL SYSTEM 失效
公开(公告)号：JPH04315217A
公开(公告)日：1992-11-06
申请号：JP8223191
申请日：1991-04-15
申请人： HITACHI LTD
发明人： IDEMOTO MANABU , HIROZAWA TOSHIO , KAMIOKA KOJI , SHIMURA TAKANORI
IPC分类号： G06F3/06 , G06F3/08
摘要： PURPOSE:To eliminate labor for exchanging a CD-ROM by loading all the CD-ROM required for a user to the CD-ROM driving device to a CD-ROM library device. CONSTITUTION:By preparing the plural CD-ROM library devices composed of plural CD-ROM drive devices 109 which can load one or plural CD-ROM, and a CD-ROM library controller 107 to control those CD-ROM driving devices, electronic mail device 116 and terminal/computer 104 for the user, the respective devices are connected with a route 101 for communication such as a telephone circuit, network and radio, etc. A user 103 retrieves CD-ROM information by connecting the terminal/computer through the route 101 for communication to the electronic mail device 116, designating an information retrieval item and transmitting the result to the CD-ROM library device, and the retrieval is achieved by transmitting the retrieved result to a place designated by the user 103.

16. 发明专利

JPH0370221A TIME DIVISIONAL MULTIPLEX RECEIVER WITH ADAPTIVE ARRAY 失效
公开(公告)号：JPH0370221A
公开(公告)日：1991-03-26
申请号：JP20461489
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE , SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO
IPC分类号： H04J3/00 , H01Q3/26 , H04B7/10 , H04B7/26 , H04L27/14
摘要： PURPOSE:To attain complicated signal processing by applying digital signal processing to the control section of an adaptive array. CONSTITUTION:Only desired one-frame of complex base band signals (I1, Q1)

17. 发明专利

JPH10154124A MICROPROCESSOR AND MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH10154124A
公开(公告)日：1998-06-09
申请号：JP31323996
申请日：1996-11-25
申请人： HITACHI LTD
发明人： KOSHIDO KOJI , YOSHIDA YUTAKA , SHIMURA TAKANORI , NAKAGAWA NORIO
IPC分类号： G06F13/18 , G06F13/368 , G06F15/16 , G06F15/167
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor which has the degree of freedom to the acquisition and release of a bus right which are performed by handshake. SOLUTION: When a microprocessor 1 is assigned to a master processor in a multiprocessor system, and when bus right release permission control information (BREQEN) is initialized to an inactive state by system reset, etc., a bus arbitrating circuit 20 nullifies a bus right release request that is externally asserted by a bus right release request signal (BREQ) arid maintains bus right release permission control information in an inactive state until required processing that is accompanied with an external bus access is completed. Thereby, it is possible to maintain a bus right independently of an external bus release request.

18. 发明专利

JPH099251A PARALLEL PICTURE ENCODING METHOD AND DEVICE THEREFOR 失效
公开(公告)号：JPH099251A
公开(公告)日：1997-01-10
申请号：JP15286095
申请日：1995-06-20
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KATO JUNICHI
IPC分类号： H04N19/102 , H04N7/24 , H04N19/00 , H04N19/107 , H04N19/136 , H04N19/172 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/46 , H04N19/463 , H04N19/503 , H04N19/51 , H04N19/517 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/80 , H04N19/82 , H04N19/91
摘要： PURPOSE: To reduce power consumption in the case of encoding dynamic images. CONSTITUTION: An image encoding device for encoding the dynamic images is provide with a valid/invalid judgement circuit 101 for storing the result of judging whether respective image blocks in one screen are valid or invalid and plural encoding processing elements 100-i for performing an encoding processing corresponding to the number of the valid blocks within one screen calculated in the valid/invalid judgement circuit 101. Then, the required encoding processing element 100-i is selected and activated from the plural encoding processing elements corresponding to the ratio of the valid blocks for which a processing amount is large.

19. 发明专利

JPH08195957A PICTURE ENCODER AND METHOD THEREFOR 失效
公开(公告)号：JPH08195957A
公开(公告)日：1996-07-30
申请号：JP545695
申请日：1995-01-18
申请人： HITACHI LTD
发明人： KATO JUNICHI , TAKIZAWA MASAAKI , SHIMURA TAKANORI , OKUMA KATSUMI
IPC分类号： H04N19/50 , G06T9/00 , H03M7/36 , H04N19/107 , H04N19/126 , H04N19/134 , H04N19/137 , H04N19/159 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/503 , H04N19/51 , H04N19/61 , H04N19/625 , H04N19/65 , H04N19/82 , H04N19/86 , H04N19/91 , H04N7/32
摘要： PURPOSE: To improve picture quality by refreshing a storage error by an intra- frame encoding system only when a moving amount is smaller than a prescribed threshold value in a block for which forced INTRA refreshing is specified. CONSTITUTION: The block picture data of 8×8 picture elements passed through a block dividing means 11 are passed through an orthogonal transformer (DCT) 14, a quantizer 15 and a variable length encoder 20 and outputted to a transmission interface. Decoded pictures passed through an inverse quantizer 16 and an inverse DCT 17 are written in a frame memory(FM) 30. An encoding mode judgement/motion vector detection means 100 reads reference pictures from the FM 30, generates a predicted error 5 in a subtractor 12 and sends it to the DCT 14 at the time of judging the encoding mode as an inter-frame encoding mode. In the block specified by a forced INTRA specifying circuit 105, the encoding mode is judged as an intra-frame encoding mode and refreshing it not based on the predicted error 5 is performed. In this case, when the moving amount 6 is larger than a prescribed threshold value, the encoding mode is judged as the inter-frame encoding mode.

20. 发明专利

JPH05292491A 失效
公开(公告)号：JPH05292491A
公开(公告)日：1993-11-05
申请号：JP9406892
申请日：1992-04-14
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KINEBUCHI YUTAKA , KANEOKA NORIYUKI
IPC分类号： H04N5/232 , H04N7/14
摘要： PURPOSE:To transmit good sized human figure images to a transmission destination by measuring the distance between a camera and the human figure and controlling the viewing angle of a zoom lens. CONSTITUTION:This method is composed of a camera 2 to which a zoom lens 37 is attached, focal distance measuring circuit 30 to measure the distance from a human figure 36 to the camera 2, and viewing angle control circuit 31 to control the viewing angle of the zoom lens. And, the viewing angle theta0 of the zoom lens 37 is set beforehand when the distance between the human figure 36 and the camera 2 is d0, for the human figure 36 to be a good size inside a display. Further, when a result (d) which the distance between the human figure 36 and the camera 2 is measured at the focal distance measuring circuit 30 is (d)=d0/2, the viewing angle control circuit 31 sets the viewing angle theta to theta=2Xtheta0. Inversely, when the result (d) which the distance between the human figure 36 and the camera 2 is measured at the focal distance measuring circuit 30 is (d)=2Xd0, the viewing angle control circuit 31 sets the viewing angle theta to be theta=theta0/2.

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