专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0370221A TIME DIVISIONAL MULTIPLEX RECEIVER WITH ADAPTIVE ARRAY 失效
公开(公告)号：JPH0370221A
公开(公告)日：1991-03-26
申请号：JP20461489
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE , SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO
IPC分类号： H04J3/00 , H01Q3/26 , H04B7/10 , H04B7/26 , H04L27/14
摘要： PURPOSE:To attain complicated signal processing by applying digital signal processing to the control section of an adaptive array. CONSTITUTION:Only desired one-frame of complex base band signals (I1, Q1)

2. 发明专利

JPH0370216A ADAPTIVE FILTER FOR ELIMINATING MULTI-PATH FADING 失效
公开(公告)号：JPH0370216A
公开(公告)日：1991-03-26
申请号：JP20461289
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO , OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE
IPC分类号： H04B7/005 , H03H21/00 , H04B1/10
摘要： PURPOSE:To process a reception data at high speed and to eliminate noise of multi-path fading at high speed by receiving information simultaneously with one bus cycle of master digital signal processing with use of a temporary storage means. CONSTITUTION:When a data is transferred from digital signal processors(DSP) 2-4 to a DSP 1, the DSP 2-4 transfer a data to first-in first-out memories(FIFO) 5, 7, 9, and it is required for the DSP 1 to read sequentially data y2-y4 from FIFOs 5, 7, 9, but when the data is transferred to the DSP 2-4, the data 20 is written from the DSP 1 in one bus cycle to the FIFOs 6, 8, 10 simultaneously. Thus, the DSP 2-4 read data from the FIFOs 6, 8, 10 simultaneously respectively. Thus, nose due to multi-path fading is eliminated at high speed.

3. 发明专利

JPH0370228A CLOCK SIGNAL REGENERATING SYSTEM 失效
公开(公告)号：JPH0370228A
公开(公告)日：1991-03-26
申请号：JP20461389
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE , SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO
IPC分类号： H04J3/06 , H04L7/02
摘要： PURPOSE:To regenerate an external data output clock from a reception signal of a data transmission channel by outputting a frame synchronizing signal, and regenerating a data output clock signal from the frame synchronizing signal. CONSTITUTION:Utilizing a ratio of a period of a frame synchronizing signal and a period of an external data outputting clock is constant in average, and only the phase of both the signals is asynchronous; the frame synchronizing signal S3 is multiplied and smoothed by a phase synchronizing circuit 8 to recover a data outputting clock CLK. Then a demodulated data series S7 is extracted of only information bit by a data conversion section 6 and outputted by a clock CLK as an external output data S0. Thus, the external data outputting clock regenerator is obtained with simple device constitution without deteriorating the utilizing rate of the frequency.

4. 发明专利

JPH0370226A FRAME SYNCHRONIZATION DETECTING CIRCUIT 失效
公开(公告)号：JPH0370226A
公开(公告)日：1991-03-26
申请号：JP20461589
申请日：1989-08-09
申请人： HITACHI LTD , YUSEISHO TSUSHIN SOGO KENK
发明人： SHIMURA TAKANORI , TSUKAMOTO NOBUO , USUI KUNITO , OKANE TAKEO , SASAOKA SHUICHI , SANPEI MASAICHI , KAMIO YUKIHIDE
IPC分类号： H04J3/06 , H04B7/02 , H04B7/26 , H04L7/08 , H04L27/14
摘要： PURPOSE:To improve the detection accuracy of a frame synchronization pattern by comparing a prescribed threshold level with a complex correlation coefficient between a reception signal at a complex base band before demodulation and a complex signal corresponding to a prescribed frame synchronization pattern of a receiver. CONSTITUTION:The circuit consists of a maximum value detection selection circuit 1 detecting and selecting a reception signal whose envelope level is maximum, a limiter circuit 2 bringing an envelope level of the reception signal into a prescribed value, a complex number correlation circuit 3 taking the complex number correlation between the reception signal and a complex number signal 6 corresponding to the specific frame synchronization pattern, a correlation coefficient arithmetic circuit 4 obtaining the correlation coefficient and a level comparator circuit 5 comparing the correlation coefficient with a frame synchronization threshold level 7. When the complex number correlation coefficient is larger than the correlation level, the reception signal is judged to be a frame synchronization pattern. Thus, the frame synchronization pattern is accurately detected.

5. 发明专利

JP2007259463A Low power processor 有权
标题翻译：低功率处理器
公开(公告)号：JP2007259463A
公开(公告)日：2007-10-04
申请号：JP2007101243
申请日：2007-04-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TOTSUKA YONETARO , ISHIBASHI KOICHIRO , MIZUNO HIROYUKI , NISHII OSAMU , UCHIYAMA KUNIO , SHIMURA TAKANORI , SEKINE ASAKO , KATSUKI YOICHI , NARITA SUSUMU
IPC分类号： H03K19/00 , G06F15/78 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/094
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit managing both a high speed and low power consumption. SOLUTION: The low power processor has a logic circuit 902 and a substrate bias control circuit 903. The logic circuit is controlled so as not to change inputs of the logic circuit after switched to a low power mode in response to the execution of an instruction. After the circuit is switched to a high-speed mode in response to an interruption, the circuit starts operation after a substrate bias voltage applied to an MOS transistor of the logic circuit has been stabilized to a predetermined level. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种管理高速度和低功耗的半导体集成电路。解决方案：低功率处理器具有逻辑电路902和衬底偏置控制电路903.逻辑电路被控制为在响应于执行方式切换到低功率模式后不改变逻辑电路的输入一个指令在电路响应于中断而切换到高速模式之后，在施加到逻辑电路的MOS晶体管的衬底偏置电压已经稳定到预定电平之后，电路开始工作。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2000298643A DATA PROCESSOR 失效
公开(公告)号：JP2000298643A
公开(公告)日：2000-10-24
申请号：JP10563999
申请日：1999-04-13
申请人： HITACHI LTD
发明人： SHIMURA TAKANORI , KATSURAGI MASAHIKO
IPC分类号： G06F13/36 , G06F5/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To facilitate the design of a peripheral device interface control circuit connected to a CPU bus. SOLUTION: Peripheral device interface circuits 120 to 123 connected to a CPU bus 103 consist of core parts 130 to 133 and variable interface blocks 140 to 143. The blocks 140 to 143 consist of a parameter register setting plural parameters corresponding to plural bus specifications that can be held by the bus 103 and an interface circuit performing an operation made to meet the specifications of the bus 103. A peripheral device interface control circuit having the same circuit structure can be used even though bus specifications requested by a CPU 102 are changed.

7. 发明专利

JPH08340495A SPLIT SCREEN DISPLAY SYSTEM 失效
公开(公告)号：JPH08340495A
公开(公告)日：1996-12-24
申请号：JP14446595
申请日：1995-06-12
申请人： HITACHI LTD
发明人： OKUMA KATSUMI , SHIMURA TAKANORI , KATO JUNICHI
IPC分类号： H04N5/45 , H04N7/14
摘要： PURPOSE: To display a new screen such as a self-portrait, etc., without impeding displays of respective images displayed in respective split screens by overwriting and displaying new screens smaller in size than each split screen on dividing lines. CONSTITUTION: A main image display control part 22 detects the dividing lines of the respective split screens and a screen control part (image reduction part 20 and self-portrait display control part 23) overwrite and display the new screen of size smaller than the respective split screens on the dividing lines. Namely, on the dividing lines of the respective split screens or on intersections of the respective split screens when the number of the split screens is three, the new screen is overwritten preferentially to display the self-portrait, etc. In this case, the displays of the respective images in the respective split screens are not impeded. If there is an unused split screen, the new screen is overwritten preferentially in the blank split screen. Further, a new screen is allocated to the entire surface of the display, and the respective split screens are reduced and allocated to positions where the image in the new screen is readable without trouble.

8. 发明专利

JPH07193202A GATE ARRAY 失效
公开(公告)号：JPH07193202A
公开(公告)日：1995-07-28
申请号：JP33051093
申请日：1993-12-27
申请人： HITACHI LTD
发明人： HATANO YUJI , KIKUCHI TAKAFUMI , HOTTA MASAO , SHIMURA TAKANORI , SHIRAISHI YOICHI , AKAZAWA TAKASHI , HIRAKI MITSURU , KIUCHI ATSUSHI
IPC分类号： H01L27/118 , H01L21/82 , H01L27/10
摘要： PURPOSE:To define the final function in an interconnection layer step after forming a chip divided at a region where a gate pattern suited to realize functions in the least areas every function block is regularly lengthwise and crosswise formed. CONSTITUTION:A base chip 101 is divided into a random logic block 111, data puss block 112, ROM block 113 and RAM block 114, each having a block- inherent gate pattern regularly arranged lengthwise and crosswise. The chip completes logic functions by adding interconnection layers. The blocks 111, 112, 113 and 114 are composed of a random logic gate pattern 121, data path gate pattern 122, data gate pattern 123 and RAM gate pattern 124, respectively.

9. 发明专利

JPH06326692A DECODER FOR ERROR CORRECTION CODE 失效
公开(公告)号：JPH06326692A
公开(公告)日：1994-11-25
申请号：JP11274293
申请日：1993-05-14
申请人： HITACHI LTD
发明人： OKUMA KATSUMI , TAKIZAWA MASAAKI , SHIMURA TAKANORI
IPC分类号： H03M13/00 , H04L1/00 , H04L7/00 , H04L7/08
摘要： PURPOSE:To detect a synchronous position at a high speed while reducing the scale of an entire device by utilizing a FIFO memory for inputting information data after error correction and detecting synchronization as a data buffer for recording synchronous pattern judged results before synchronization is established and in the case of step-out of synchronization. CONSTITUTION:When the step-out of a frame synchronization is detected by a frame synchronization monitoring part 31 or when it is required to obtain frame synchronization such as immediately after the reset of a circuit or the like, an error correction control part 35 sends signals for indicating to the effect that the detection of the frame synchronization is performed to a frame synchronization detection part 34, the frame synchronization monitoring part 31 and an error correction circuit 32. Also, the signals for indicating to the effect that the frame synchronization is being detected are sent to a code memory 33 as well and the frame synchronization detection part 34 uses the code memory 33 as a memory for detecting the frame synchronization. While the synchronization is detected, the error correction circuit 32 does not correct errors and does not write data to the code memory 33.

10. 发明专利

JPH04315217A CD-ROM LIBRARY CONTROL SYSTEM 失效
公开(公告)号：JPH04315217A
公开(公告)日：1992-11-06
申请号：JP8223191
申请日：1991-04-15
申请人： HITACHI LTD
发明人： IDEMOTO MANABU , HIROZAWA TOSHIO , KAMIOKA KOJI , SHIMURA TAKANORI
IPC分类号： G06F3/06 , G06F3/08
摘要： PURPOSE:To eliminate labor for exchanging a CD-ROM by loading all the CD-ROM required for a user to the CD-ROM driving device to a CD-ROM library device. CONSTITUTION:By preparing the plural CD-ROM library devices composed of plural CD-ROM drive devices 109 which can load one or plural CD-ROM, and a CD-ROM library controller 107 to control those CD-ROM driving devices, electronic mail device 116 and terminal/computer 104 for the user, the respective devices are connected with a route 101 for communication such as a telephone circuit, network and radio, etc. A user 103 retrieves CD-ROM information by connecting the terminal/computer through the route 101 for communication to the electronic mail device 116, designating an information retrieval item and transmitting the result to the CD-ROM library device, and the retrieval is achieved by transmitting the retrieved result to a place designated by the user 103.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式