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11. 发明专利

JP2007280606A Dram chips 有权
标题翻译： DRAM芯片
公开(公告)号：JP2007280606A
公开(公告)日：2007-10-25
申请号：JP2007183074
申请日：2007-07-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/4074 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To especially reduce an active standby current by achieving low power consumption of a power supply circuit of a semiconductor memory. SOLUTION: A DRAM chip is provided with a first voltage supply means for supplying a first voltage to a plurality of sense amplifiers and a second voltage supply means for supplying a second voltage to a column decoder. The first voltage supply means includes a plurality of first voltage limiter circuits arranged in the number same as the number of plurality of memory banks correspondingly to each of the memory banks and a second voltage limiter circuit whose current supply capability is smaller than that of the first voltage limiter circuit. The second voltage supply means includes: a third voltage limiter circuit; a fourth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output node of the third voltage limiter circuit; and a fifth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output nodes of the third and fourth voltage limiter circuits. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过实现半导体存储器的电源电路的低功耗来特别地降低主动待机电流。解决方案：DRAM芯片设置有用于向多个读出放大器提供第一电压的第一电压供应装置和用于向列解码器提供第二电压的第二电压供应装置。第一电压供给装置包括多个与每个存储体相对应的多个存储体的数量相同的第一限压器电路;以及第二限压器电路，其电流供应能力小于第一限压电路。第二电压供给装置包括：第三限压器电路; 第四限压电路，其电流供给能力小于第三限压电路，其输出节点连接到第三限压电路的输出节点; 以及电流供给能力小于第三限压电路的第五限压电路，其输出节点连接到第三和第四限压器电路的输出节点。版权所有（C）2008，JPO＆INPIT

12. 发明专利

JP2004259431A Dram 有权
公开(公告)号：JP2004259431A
公开(公告)日：2004-09-16
申请号：JP2004112616
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/407 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To reduce the electric power consumption of the power source circuit of a semiconductor memory, and more particularly, to reduce the standby current thereof. SOLUTION: A DRAM (dynamic RAM) is equipped with a plurality of memory banks which can be activated by respective activation commands and a plurality of power supply circuits which are disposed in corresponding to the respective memory banks, respectively receive external power supply voltages and output internal power supply voltages. The outputs of the power supply circuits are respectively connected to the corresponding memory banks and turn on the power source circuit component in correspondence to one of the memory banks among the power source circuits in response with the command for activating the memory bank and turn off the remaining power source circuits. COPYRIGHT: (C)2004,JPO&NCIPI

13. 发明专利

JP2004213895A Semiconductor device 有权
公开(公告)号：JP2004213895A
公开(公告)日：2004-07-29
申请号：JP2004112617
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of a power supply circuit of a semiconductor memory and to reduce an active standby current in particular.
SOLUTION: A plurality of memory banks that can be respectively and independently activated by an activation command and a plurality of power supply circuits provided respectively corresponding to the memory banks to respectively receive external power source voltage and output a prescribed internal power source voltage are provided. Outputs of the power supply circuits are respectively connected to corresponding memory banks, a power supply circuit provided in accordance with a corresponding bank among the power supply circuits are turned on in a response to a command for activating one of the memory banks, and the other power supply circuits are turned off.
COPYRIGHT: (C)2004,JPO&NCIPI

14. 发明专利

JP2004146054A Semiconductor device 审中-公开
公开(公告)号：JP2004146054A
公开(公告)日：2004-05-20
申请号：JP2003390050
申请日：2003-11-20
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMURA MASAYUKI , MIYAZAWA KAZUYUKI , IWAI HIDETOSHI
IPC分类号： H01L27/088 , G11C11/401 , G11C11/408 , H01L21/8234 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device achieving a large storage capacity of a memory array formed by disposing dynamic type memory cells in a matrix shape and improvement of its refreshment characteristics.
SOLUTION: A back bias voltage optimum for the refreshment characteristics and low in absolute voltage is supplied to a P type well part wherein a memory array part formed by disposing the dynamic type memory cells in a matrix shape is formed and back bias voltage against undershoot voltage and high in absolute voltage is supplied to a P type well part wherein an N channel type MOS FET (metal oxide semiconductor field effect transister) of an input or output circuit connected to an external terminal is formed.
COPYRIGHT: (C)2004,JPO

15. 发明专利

JPH11348844A CRAWLER BELT 失效
公开(公告)号：JPH11348844A
公开(公告)日：1999-12-21
申请号：JP16178198
申请日：1998-06-10
申请人： HITACHI LTD
发明人： HATTORI TOSHIO , KOMATSUBARA MASAAKI , SAKATA SHOJI , NAKAMURA MASAYUKI , UMEZAWA SADAO
IPC分类号： E02F9/02 , B62D55/21 , B62D55/215
摘要： PROBLEM TO BE SOLVED: To reduce the shock load and noise during traveling by connecting adjacent chain links with pins, providing annular elastic bodies on the outer periphery of each pin and the inner periphery of the holes of the chain links, and providing annular bodies with rigidity larger than that of the annular elastic bodies on the inner periphery of the holes. SOLUTION: Chain links 2, 2' adjacent to a pin 1 are connected by the pin 1 inserted into the holes formed on them to constitute a crawler belt. A plurality of rubber rings 3 which are annular elastic bodies are pressed in between the pin 1 and the chain link holes at intervals in the axial direction. Annular metal bushes 4 with rigidity larger than that of the rubber rings is inserted between the outer periphery of the pin 1 and the adjacent rubber rings 3 at the gap δwith the inner peripheral face of the chain link holes. A load is applied between the pin 1 and the chain links 2, the metal bushes 4 share the load when the relative displacement exceeds the gap δ of the metal bushes 4, thus rigidity can be increased.

16. 发明专利

JPH11339473A METHOD FOR ALLOTTING GLOBAL I/O LINE, AND SEMICONDUCTOR MEMORY APPARATUS, AND DATA-PROCESSING APPARATUS 失效
公开(公告)号：JPH11339473A
公开(公告)日：1999-12-10
申请号：JP14914598
申请日：1998-05-29
申请人： HITACHI LTD
发明人： YAHATA HIDEJI , FUJISAWA HIROKI , NAKAMURA MASAYUKI
IPC分类号： G11C11/409 , G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a technique for restricting an increase of a delay time at a global I/O line part because of a change in word organization. SOLUTION: Coping with a change in word organization, a global I/O line (GIO0, GIO1, GIO2,...) is divided into a read system and a write system. Allocation of the global I/O line to an input/output is changed, thereby reducing a burden. Moreover, an increase in delay time at the global I/O line is restricted. The semiconductor memory apparatus is accordingly sped up in operation.

17. 发明专利

JPH11144458A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11144458A
公开(公告)日：1999-05-28
申请号：JP30209397
申请日：1997-11-04
申请人： HITACHI LTD
发明人： FUJISAWA HIROKI , NARUI SEIJI , NAKAMURA MASAYUKI
IPC分类号： G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce a charge/discharge current produced by the parasitic capacitance of a wiring in a hierarchical word line structure, reduce a power consumption substantially and, further, reduce a layout area. SOLUTION: The levels of the driving signal and selection signal of a main word driver 9a are transformed from power supply voltages VCC into step-up power supply voltages VPP by level transformation circuits 9b, and 9b2 respectively in a main word driver unit 9. Then the driving signal and the selection signal are outputted to a sub word driver 10 through a main word line MWL and a selection signal line FX. The sub word driver 10 has a level transformation function which steps down a low voltage level at the determination of the amplitude of a sub word line SWL from a ground voltage VSS to a negative voltage VNN of about -1.0 V and the amplitude of the sub word line SWL is determined within the range of the step-up power supply voltage VPP- the negative voltage VNN.

18. 发明专利

JPH11132048A VARIABLE CAPACITY TYPE SUPERCHARGER 失效
公开(公告)号：JPH11132048A
公开(公告)日：1999-05-18
申请号：JP29670297
申请日：1997-10-29
申请人： HITACHI LTD
发明人： NAKAMURA MASAYUKI
IPC分类号： F02B37/00 , F01D25/00 , F02B37/24
摘要： PROBLEM TO BE SOLVED: To reduce resistance force acting on a rotational ring and to prevent abrasion and creep deformation of a contact surface between a link plate and a notch, by placing a rotational ring provided with a notch engaging with a link plate around its rotation shaft, and by providing three projections on the outer surface of the rotational ring. SOLUTION: A link plate 3 for giving torque is mounted to a rotation shaft 2 of a movable nozzle vane 1, a rotational ring 4 provided with a notch engaging with this link plate 3 is placed so as to cover the rotation shaft 2, and projections are formed at three positions on the outer peripheral surface of the rotational ring 4. When counterclockwise force orthogonal to the projections is acted on the rotational ring 4, the rotational ring 4 moves in the load direction, the projections collide against the inner peripheral surface 7 of the casing, moment in the load direction acts to the rotational ring 4. But, when angle of each projection is larger than 90 deg., only force formed by subtracting inertia force from frictional force on a contact surface acts to the ring. Thus, abrasion and creep deformation of a contact surface between the link plate 3 and the notch are restrained.

19. 发明专利

JPH10117468A ROTOR FOR DYNAMO-ELECTRIC MACHINE 失效
公开(公告)号：JPH10117468A
公开(公告)日：1998-05-06
申请号：JP26826696
申请日：1996-10-09
申请人： HITACHI LTD
发明人： NAGASHIMA HIDEAKI , NAKAMURA MASAYUKI , NAGAI HIROKI , IMAI ISATO
IPC分类号： H02K1/26 , H02K17/16
摘要： PROBLEM TO BE SOLVED: To provide the rotor structure of a dynamo-electric machine which can meet thermal expansion, stresses due to centrifugal force, and stresses generated at an end ring and a retaining ring at the time of stopping by forming it into an arc-shaped groove annular ring shape near the fitting part of the end ring. SOLUTION: A rotor bar 12 is fitted into the slot of a rotor core 8, having a slot in the axial direction. An end ring 9 is fitted at the end of a rotor bar 12, and a retaining ring 13 is fitted at the outer periphery of the end ring 9. At the end ring 9 and the retaining ring 13, an arc-shaped groove 14 is cut into an annular shape. An arc-shaped groove is formed at a surrounding part near the fitting part of the rotor bar 12, by which it is possible to reduce the stress concentration near the fitting part of the rotor bar 12 by thermal expansion and centrifugal force, as well as the stresses generated at the end ring and the retaining ring at the time of stopping a dynamo-electric machine.

20. 发明专利

JPH09204774A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09204774A
公开(公告)日：1997-08-05
申请号：JP19242996
申请日：1996-07-22
申请人： HITACHI LTD , TEXAS INSTRUMENTS INC
发明人： AKIBA TAKESADA , OTORI HIROSHI , NAKAMURA MASAYUKI , EIDEIN II HISUROTSUPU
IPC分类号： G11C11/406 , G11C11/407 , G11C11/409 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To reduce a peak current related to all bit mats at the time of CBR (column address strobe before row address strobe) refresh operation of a DRAM. SOLUTION: This memory is provided with a CBR control circuit 78 detecting the CBR refresh operation. When CBR refresh is detected, the amplification of the bit mats MAT1, MAT2 are shifted each other, and the times when respective bit mats MAT1, MAT2 flow peak current through are made to alternate. In a form of another execution, when the CBR refresh is detected, word lines WL1, WL2 are shifted each other and made active, and thus, the times when respective bit mats MAT1, MAT2 pass the peak current through are made alternative.

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