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11. 发明专利

JP2005260258A Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：JP2005260258A
公开(公告)日：2005-09-22
申请号：JP2005113818
申请日：2005-04-11
申请人： Hitachi Ltd , Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOSHIHIRO , TADAKI YOSHITAKA , KAWAKITA KEIZO , MURATA JUN , YUHARA KATSUO , TANAKA MICHIO , KAKIZAKI TAKATOSHI , SAKAI TAKESHI , KUMAI TOSHIKAZU , NISHIMURA MICHIO , SAITO KAZUHIKO , KAERIYAMA TOSHIYUKI , CHO SEISHIYU
IPC分类号： G03F1/30 , G03F1/36 , G03F1/54 , H01L21/027 , H01L21/8242 , H01L27/108 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To exactly transfer the shape and the dimension of a transfer pattern to a design pattern when a given pattern is transferred by using a photomask having a phase shifter. SOLUTION: When a bit line of a DRAM is transferred, a photomask PM2 is used, in which a plurality of light transmission regions P4 are arranged along a predetermined direction, and phase shifters PS4 are arranged in every other row of the plurality of light transmission regions P4 which are arrayed in the predetermined direction. Each light transmission region P4 has a broad region and a strip region. A light shielding region S1 is arranged in the broad region, and auxiliary patterns PA2 are formed near the boundary region between the broad region and the strip region of the light transmission regions P4 in the light shielding regions surrounding the light transmission regions P4. The auxiliary pattern PA2 is formed of a fine light transmission region by which the light of the opposite phase to the light transmitting the light transmission regions P4 is formed. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：当通过使用具有移相器的光掩模传送给定图案时，将转印图案的形状和尺寸精确地转印成设计图案。解决方案：当DRAM的位线被传送时，使用光掩模PM2，其中沿着预定方向布置多个光透射区域P4，并且移位器PS4布置在多个的每隔一行中的沿着预定方向排列的光透射区域P4。每个透光区域P4具有宽的区域和条带区域。遮光区域S1布置在宽区域中，并且辅助图案PA2形成在围绕光透射区域P4的遮光区域中的透光区域P4的宽区域和带状区域之间的边界区域附近。辅助图案PA2由形成与透光区域P4相反的相反相位的光的细光透射区域形成。版权所有（C）2005，JPO＆NCIPI

12. 发明专利

JPH08241970A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241970A
公开(公告)日：1996-09-17
申请号：JP6474596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MURATA JUN , TADAKI YOSHITAKA , KANEKO HIROKO , SEKIGUCHI TOSHIHIRO , UCHIYAMA HIROYUKI , NAKAMURA TAKASHI , MAEDA TOSHIO , KASAHARA OSAMU , ENAMI HIROMITSU , OGISHIMA JUNJI , NAGAO MAKI , FUNAHASHI TOMOMASA , KIGUCHI YASUO , KOJIMA MASAYUKI , KOIKE ATSUYOSHI , MIYAZAWA HIROYUKI , SADAOKA MASATO , KADOTA KAZUYA , CHIKAWAHARA TADASHI , NOJIRI KAZUO , KOBAYASHI YUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which reduces a disconnection defect or the like in the stepped part of the interconnection of a word line for a shunt by a method wherein a memory cell in a first region and a memory cell in a second region are connected by a common gate electrode in such a way that respective word lines are connected across both regions and a conductive layer which is the same layer as the electrode of a capacitance element is formed across both regions. CONSTITUTION: MISFET's Qs's for memory selection of a plurality of memory cells M are constituted on the main face part of p-well regions 22, and they are constituted mainly of the p-well regions 22, of gate insulating films 25, of gate electrodes 26 and of one pair of n-type semiconductor regions 28 as a source region and a drain region. The gate electrodes 26 and word lines 26 are formed respectively of the same conductive layer, and the word lines connect the respective gate electrodes 26 of the MISFET's for Qs's for memory selection of the plurality of memory cells M arranged in the row direction. In addition, n-type semiconductor regions 28 on the connection side of capacitance elements C, for information storage, of the MISFET's Qs's for memory selection are constituted integrally with n semiconductor regions 33A.

13. 发明专利

JPH02192168A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02192168A
公开(公告)日：1990-07-27
申请号：JP973689
申请日：1989-01-20
申请人： HITACHI LTD
发明人： MURATA JUN
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
摘要： PURPOSE:To reduce a MISFET in occupying area and to improve a semiconductor integrated circuit device in the degree of integration by a method wherein the MISFET is composed of a fine groove formed on the primary face of a channel forming region of a semiconductor substrate, a gate electrode, a source region, a drain region, and an electric field relaxation semiconductor region. CONSTITUTION:A MISFET is composed of a fine groove 2 formed on the primary face of a channel forming region of a semiconductor substrate 1, a gate electrode 4 formed inside the fine groove 2 self-aligned with the fine groove 2 through the intermediary of a gate insulating film, a source region and a drain region 7 formed self-aligned with the gate electrode 4, and an electric field relaxation semiconductor region formed on the primary face between the source or the drain region and the channel forming region. Therefore, the MISFET can be reduced in occupied area by the extent of the dimensional margin of a mask between the gate electrode 4 and the fine groove 2 in a manufacturing process. By this setup, a semiconductor integrated circuit device can be improved in a degree of integration and pn junction breakdown strength through the electric field relaxation region 5.

14. 发明专利

JPS6480068A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480068A
公开(公告)日：1989-03-24
申请号：JP23591487
申请日：1987-09-19
申请人： HITACHI LTD
发明人： MURATA JUN
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To increase the charge accumulation capacitance of a capacitor as well to contrive reduction of a soft error by a method wherein the area of the electrode layer of the capacitor, to be used for information accumulation utilizing the extended space of the selective signal line, in increased in a DRAM. CONSTITUTION:A DRAM memory cell M is composed of a cell selecting MISFETQs and an information accumulating capacitor C of a stacked structure. In this DRAM memory cell, a set of complementary data line DL and a selective signal line YSL, with which said data line DL will be selected, are extended in the same direction. Then, the lower side electrode layer 13, constituting the above-mentioned capacitor C, is extended to the position where the electrode layer 13 will be overlapped with the selective signal line YSL. As a result, the area of the lower side electrode layer of the information accumulating capacitor C can be increased, the amount of the charge accumulation of the capacitor can also be increased, and the soft error of the DRAM can be reduced.

15. 发明专利

JPS6480067A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6480067A
公开(公告)日：1989-03-24
申请号：JP23591087
申请日：1987-09-19
申请人： HITACHI LTD
发明人： SAGAWA MASAKAZU , MURATA JUN , SHIMIZU SHINJI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To prevent the generation of a soft error in a memory cell mode by a method wherein, a potential barrier layer is provided under the semiconductor region on the side where it is connected to the information accumulation capacitor of a FET, to be used for memory selection, in a DRAM. CONSTITUTION:A DRAM memory cell M is composed of a memory cell selecting MISFETQs and an information storing capacitor C. A potential barrier layer 4B, which is formed by diffusing impurities and a channel stopper region 4A will be formed thereon, is provided under one semiconductor region 9 located on the side where it is connected to the capacitor C of the above-mentioned FETQs. Also, said channel stopper region 4A and the potential barrier layer 4B are formed in the same manufacturing process. As the minor carrier captured by the above-mentioned information storing capacitor can be reduced through the above-mentioned procedures, the generation of a soft error of a memory cell mode can be prevented, and the number of manufacturing processes can also be reduced.

16. 发明专利

JPS6480065A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480065A
公开(公告)日：1989-03-24
申请号：JP23590687
申请日：1987-09-19
申请人： HITACHI LTD
发明人： MURATA JUN , TADAKI YOSHITAKA
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To contrive improvement in information holding characteristics by a method wherein, in a DRAM memory cell, the semiconductor region on the side where the information storing capacitor of a cell selecting FET is connected, is composed of the material into which low impurity concn. ions are implanted. CONSTITUTION:A DRAM memory cell M is composed of the MISFETQs for memory cell selection and the information memorizing capacitor C of stacked structure, and MISFETQn and Qp constituting a circumferential circuit are formed on the same substrate. Then, the semiconductor region 9 on the side where the capacitor C of said FETQs will be connected is composed of the region into which ions of the impurity concn. lower than that of the semiconductor region 17 of the FETQn, constituting the circumferential circuit, are implanted. As a result, the leak of accumulated load is reduced, and the information holding characteristics of the DRAM can be improved.

17. 发明专利

JPS6480061A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6480061A
公开(公告)日：1989-03-24
申请号：JP23591387
申请日：1987-09-19
申请人： HITACHI LTD
发明人： SEKIGUCHI TOSHIHIRO , MURATA JUN , KANEKO HIROKO , SHIMIZU SHINJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To contrive improvement in the dielectric withstand voltage of a dielectric film by a method wherein the dielectric film of the capacitor for accumulation of information of stacked structure of a DRAM is constituted in the same form as the upper layer of the second electrode layer. CONSTITUTION:A DRAM is composed of a MISFET Qs for selection of a memory cell and a capacitor C for accumulation of information. Said capacitor C is composed of a stacked structure in which the first electrode layer 13, a part of which is connected to the semiconductor region 9 of the above-mentioned FET Qs, a dielectric 14 and the second electrode layer 15 are successively laminated. The dielectric film 14 and the second electrode layer 15 are formed in the same shape. As the charge accumulation on the dielectric film 14 is reduced through the above-mentioned procedures, the dielectric withstand voltage of the dielectric film can be improved. Also, in the process of manufacture of the title device, the inter-layer insulating film 12 on the other semiconductor region of the above-mentioned FET Qs for memory selection is removed using the above-mentioned second electrode layer 15 or the mask with which the layer 15 is patterned. As a result, the reduction in number of manufacturing process can be accomplished.

18. 发明专利

JPS61152054A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61152054A
公开(公告)日：1986-07-10
申请号：JP27281884
申请日：1984-12-26
申请人： HITACHI LTD
发明人： MURATA JUN , KOIKE JUNICHI , FUJITA MINORU
IPC分类号： H01L27/00 , H01L21/768 , H01L21/8238 , H01L27/06 , H01L27/092
摘要： PURPOSE:To establish an ohmic contact without enhancing the concentration of impurities in N type and P type semiconductor regions by a method wherein a high-melting point metal silicide layer is formed between the semiconductor regions of two MISFET elements of different conductivity types in a complementary three-dimensional MISFET device. CONSTITUTION:On the primary surface of a substrate 1, element activation regions are formed, surrounded by a relatively thick SiO2 film serving as a field insulating layer, and N-channel MOSFETs are built in the element activation regions. In the diffusion layers of the source 3 and drain 4 of the N-channel MOSFETs, high-melting point metal silicide layers 5 are formed, respectively. The N-channel MOSFETs are isolated from P-channel MOSFETs by insulating films 8. The insulating films 8 also serve as gate insulating films for the P- channel MOSFETs and are locally provided with holes wherein ohmic contact is established between P-channel MOSFET drain regions 10 and N-channel MOSFET source regions 3 with the intermediary of the high-melting point meal silicide layers 5.

19. 发明专利

JP2567873B2 失效
公开(公告)号：JP2567873B2
公开(公告)日：1996-12-25
申请号：JP23591487
申请日：1987-09-19
申请人： HITACHI LTD
发明人： MURATA JUN
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108

20. 发明专利

JPH0774164A SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0774164A
公开(公告)日：1995-03-17
申请号：JP17315794
申请日：1994-07-04
申请人： HITACHI LTD
发明人： MIURA HIDEO , OGASAWARA MAKOTO , MASUDA HIROO , MURATA JUN , OKAMOTO NORIAKI
IPC分类号： H01L21/76 , H01L21/316 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To provide a device structure and a method of its manufacture wherein the dimensions of element formation regions and element isolation regions within a semiconductor device are defined to prevent dislocation in forming such element isolation regions by thermal oxidation of the device's silicon substrate. CONSTITUTION:In forming element isolation regions on a semiconductor substrate 1 with a thermal oxidation film, the width L of a silicon nitride film for the protection of element formation regions and the width S of element isolation regions encircling the element formation regions, are defined according to the depth D of shallow grooves that are formed on the silicon substrate surface at the time of patterning the silicon nitride film before thermal oxidation.

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