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11. 发明专利

JPH1131947A FLIP-FLOP CIRCUIT AND CLOCK SYNCHRONIZATION SYSTEM USING THE CIRCUIT 失效
公开(公告)号：JPH1131947A
公开(公告)日：1999-02-02
申请号：JP18624897
申请日：1997-07-11
申请人： HITACHI LTD
发明人： TANAKA KATSUYA , KATO TAKESHI , YAMASHITA HIROKI , YAGYU MASAYOSHI , SAITO TATSUYA
IPC分类号： H03K5/00 , H03K3/037
摘要： PROBLEM TO BE SOLVED: To provide a flip-flop circuit which has small variation in delay time even if a setup time varies. SOLUTION: After an input signal reaches N2 from N1 by turning off a transfer gate TG1, transfer gates TG2 and TG3 are turned on and TG4 is turned off to determine the levels of the signal at N1 and N2; and then TG2 is turned on to reduce variation in delay time after the TG2 is turned on.

12. 发明专利

JPH09148908A TWO-WAY INTERFACE CIRCUIT 失效
公开(公告)号：JPH09148908A
公开(公告)日：1997-06-06
申请号：JP29954395
申请日：1995-11-17
申请人： HITACHI LTD
发明人： SAITO TATSUYA , YAMASHITA HIROKI , NAKANISHI KEIICHIRO , ITOU HIROYUKI
IPC分类号： H03K19/0185 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To realize an interface circuit of low power consumption with a small number of elements. SOLUTION: Input/output terminals of interface circuits 101 and 102 are mutually connected by a signal line 103 and are used. Circuits 1013 and 1023 change control potentials Vg1 and Vg2 given to receiver circuits. FETs 1014 and 1024 are used in receiver circuits 1012 and 1022, and their gate electrodes are connected to control potentials Vg1 and Vg2, and their source electrodes are connected to the signal line 103. Signals Vin1 and Vin2 inputted to driver circuits 1011 and 1021 are inputted to control circuits 1013 and 1023 in the same manner. Drain currents corresponding to potential differences between gates and sources are obtained by this constitution. Obtained drain currents are converted to signal levels required in the circuit in the next stage by FETs 1015 and 1025 and are outputted to terminal Vout1 and Vout2.

13. 发明专利

JPH07135223A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07135223A
公开(公告)日：1995-05-23
申请号：JP14593293
申请日：1993-06-17
申请人： HITACHI LTD
发明人： USAGAWA TOSHIYUKI , YAMASHITA HIROKI , IMAMURA YOSHINORI
IPC分类号： H01L29/812 , H01L21/338 , H01L27/095
摘要： PURPOSE:To keep a drain region free from the effect of contact resistance of various junctions by a method wherein the drain region or a source region and a gate defined in length by a specific formula are set in length as prescribed. CONSTITUTION:A gate capacitance per unit area is a few times as large as a drain capacitance per unit area, so that the length L (mum) of the drain region is set to range from Lg to 2Lg (Lg is length of a gate region), whereby the drain region can be set small in capacitance. The length of the drain region is set larger than Lmin (mum) represented by a formula. The length Lg of the gate is set to Lmin defined by a formula (rhoc is total sum of contact resistivity of materials), and the length L of the drain region is designed as large as nearly Lmin to 2Lmin, whereby a drain region can be designed 1/3 to 1/10 as large in capacitance as a gate region.

14. 发明专利

JPH053421A FLIP-FLOP CIRCUIT 失效
公开(公告)号：JPH053421A
公开(公告)日：1993-01-08
申请号：JP31222791
申请日：1991-11-27
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , ITOU HIROYUKI , TANAKA HIRONORI , KAWADA ATSUMI , NAGAI KENJI , YOSHIHARA KAZUHIRO , IMAIZUMI ICHIRO
IPC分类号： H03K3/037
摘要： PURPOSE:To form the flip-flop circuit operated at a high speed by providing a drive gate including a tri-state gate controlled by a clock signal and a storage section storing its output potential to the flip-flop circuit so as to reduce a delay time till the clock signal is switched. CONSTITUTION:Tri-state gates 101, 102 act like inverters independently of an output level of inverters 103,104 when a clock signal CKB is at a low level and output inverse of signals with respect to data signals DT, DB inputted respectively. On the other hand, when the clock signal CKB reaches a high potential, the output of the gates 101, 102 reaches a high impedance state regardless of the potential of the data signals DT, DB and the output is opened. In this case, the signals QT, QB are kept to be a state before the clock signal CKB is switched by the inverters 103, 104 of a storage section 106. Thus, the delay time till the clock signal is selected is reduced.

15. 发明专利

JPH0476610A CLOCK DISTRIBUTING SYSTEM 失效
公开(公告)号：JPH0476610A
公开(公告)日：1992-03-11
申请号：JP18393090
申请日：1990-07-13
申请人： HITACHI LTD
发明人： IGASHIRA HIROYUKI , TANAKA HIRONORI , YAMASHITA HIROKI
IPC分类号： G06F1/10
摘要： PURPOSE:To obtain a clock signal whose skew in a chip is very small by changing the delay time in accordance with the output of a phase comparing circuit by a clock distributing circuit, which distributes a clock signal to one area, in the vicinity of the boundary of areas. CONSTITUTION:Small areas 140 and 141 where phases of clock signals should be compared are adjacent. Consequently, a phase comparing circuit 131 which compares phases of two clock signals with each other to output the result can be arranged in the vicinity of the boundary between small areas 140 and 141. As the result, proper flip flop groups 320 and 321 in small areas 140 and 141 are selected to input them to the phase comparing circuit 131 without extending connection lines 310 and 311. A delay control circuit changes the delay time of a distributing circuit 121 with variable delay circuit by a control signal 303.

16. 发明专利

JPH03220818A LOGIC CIRCUIT 失效
公开(公告)号：JPH03220818A
公开(公告)日：1991-09-30
申请号：JP19487190
申请日：1990-07-25
申请人： HITACHI LTD
发明人： KAWADA ATSUMI , YAMASHITA HIROKI , TANAKA HIRONORI , ITOU HIROYUKI , YOSHIHARA KAZUHIRO , YAMADA MINORU
IPC分类号： G05F3/24 , H03K19/0952
摘要： PURPOSE:To form a high speed circuit with less dispersion in the delay time by applying a prescribed voltage to a pre-stage of load element so as to reduce the dispersion in the current flowing to pre-stage logic and a current flowing to a load drive section. CONSTITUTION:Logic circuits 100, 200 are operated by a positive power supply 151 and a negative power supply 153 and a prescribed level Vg is applied to a gate of a logic load element (FET 603). The FET 603 is made up of a normally-on FET. A current flowing to the FET 603 is a value proportional to (Ygs-Vth) , where Vgs is a gate-source voltage and Vth is a threshold voltage. Since the Vth is negative in the normally-on FET, the value of Vgs-Vth is increased, Thus, a dispersion Vth of the Vth takes place, the effect is relatively decreased.

17. 发明专利

JPS62268208A LEVEL SHIFT CIRCUIT 失效
公开(公告)号：JPS62268208A
公开(公告)日：1987-11-20
申请号：JP11076786
申请日：1986-05-16
申请人： HITACHI LTD
发明人： MASUDA NOBORU , YAMASHITA HIROKI , TANAKA HIRONORI
IPC分类号： H03K5/003 , H03K5/00 , H03K19/00 , H03K19/0185
摘要： PURPOSE:To compensate the change in the circuit characteristic due to temperature change without using a control signal by adding a source follower circuit whose level shift quantity is increased as temperature rises to a diode in a level shift circuit for a semiconductor integrated circuit. CONSTITUTION:Gate and source of elements whose current is increased as temperature rises, e.g., normally-on type FETs 1, 2 having not so much threshold voltage are connected in common in the source follower circuit and the components are used as a load. The level shift of the source follower circuit is selected as nearly -1 time of the threshold voltage of the FETs 1, 2 so that the change in the level shift of the source follower circuit and the change in the forward voltage drop of the diode are just cancelled. That is, gate widths W1, W2 of the FETs 1, 2 are designed to be W2=4W1. As a result the temperature change of Vf, Vt is cancelled together and a voltage difference Vi-Vo between an input terminal 100 and an output terminal 101 is made nearly constant independently of the temperature.

18. 发明专利

JPS6297366A GAAS INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6297366A
公开(公告)日：1987-05-06
申请号：JP14038985
申请日：1985-06-28
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , TANAKA HIRONORI , HAYASHI TAKEHISA , KODERA NOBUO
IPC分类号： H01L29/93 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L27/095 , H01L29/47 , H01L29/872 , H03K5/003 , H03K19/0175
摘要： PURPOSE:To decrease parasitic capacitance, by providing an electrode or a wiring, which is connected to the cathode electrode of a diode, between the anode of the diode and an element or a wiring, which is arranged in the vicinity of the diode. CONSTITUTION:This device is composed of a GaAs substrate 510, an interlayer insulating film 509, a cathode electrode 501 of a diode, which is used as a coupling capacitor, and a metal wiring 506, which is connected to the electrode 501. A numeral 502 indicates the anode electrode of the diode, a numeral 504 an N-type active layer and a numeral 503 an N high concentration active layer. The electrode 501 is ohmic-contacted with the active layers 503 and 504. The electrode 502 forms a Schottky junction together with the active layer 503. A numeral 505 indicates a metal wiring, which is arranged in the vicinity of the diode. The shielding wiring 506 is contacted with the electrode 501 through a contact hole 507 and contacted with the GaAs substrate 510 through a contact hole 508. In this structure, parasitic capacitance between the metal wiring 505 and the anode electrode 502 of the diode can be decreased, and the area of the diode can be decreased.

19. 发明专利

JPS59215737A High speed signal measuring device 失效
标题翻译：高速信号测量装置
公开(公告)号：JPS59215737A
公开(公告)日：1984-12-05
申请号：JP8912483
申请日：1983-05-23
申请人： Hitachi Ltd
发明人： DOI TOSHIO , HAYASHI TAKEHISA , YAMASHITA HIROKI , TANAKA HIRONORI , MASAKI AKIRA
IPC分类号： G01R31/26 , G01R1/073 , H01L21/66 , G01R21/07
CPC分类号： H01L22/00
摘要： PURPOSE:To enable to fit a by-pass capacitor without reducing the number of pieces of microstripe lines at a prober by a method wherein the chip capacitor is fitted to the earthed face side of a probe card. CONSTITUTION:Transmission lines are formed of microstripe lines 13. Accordingly the face on the opposite side from the surface fitted with the probes 15 of a probe card 11 is made as the earthed face. An opening part 18 formed at the center of a mount 17 fixed with the card 11 is made larger than the opening part 19 of the card 11, and the earthed face of the card 11 is exposed from the mount 17 in the neighborhood of the center. The metal film of the earthed face of the exposed part 20 thereof is removed to expose the insulator substrate of the card 11, the electrode on one side of a chip capacitor is connected to the earthed face, and the probe 15 of the electric source line and the chip capacitor are connected. By fitting the chip capacitor to the earthed face on the opposite side from the surface provided with the signal lines in such a way, to reduce the number of the microstripe lines 13 for fitting of the by-pass capacitor is not necessitated.
摘要翻译：目的：为了能够在旁路电容器中安装旁路电容器，而不会通过其中芯片电容器安装到探针卡的接地面侧的方法，而不减少探测器的微带线数量。构成：传输线由微带线13形成。因此，与装配有探针卡11的探针15的表面相对的一侧的面被制成接地面。形成在与卡11固定的安装件17的中心的开口部18比卡11的开口部19大，并且卡11的接地面从中心附近的安装件17露出。去除暴露部分20的接地面的金属膜，露出卡片11的绝缘体基板，将片状电容器一侧的电极连接到接地面，电源线的探针15 并连接片式电容器。通过以这样的方式将片状电容器装配到与设置有信号线的表面相对的接地面上，为了减少用于配合旁路电容器的微带线13的数量，不是必需的。

20. 发明专利

JP2013021543A Transimpedance amplifier, semiconductor device and optical communication module 有权
标题翻译：放大放大器，半导体器件和光通信模块
公开(公告)号：JP2013021543A
公开(公告)日：2013-01-31
申请号：JP2011153933
申请日：2011-07-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKEMOTO KYOJI , YAMASHITA HIROKI , TSUJI SHINJI
IPC分类号： H03F1/26 , H03F3/08 , H04B10/40 , H04B10/50 , H04B10/60
CPC分类号： H03F3/085 , H03F1/0222 , H03F1/0233 , H03F1/083 , H03F3/087 , H03F2200/372 , H03F2200/504 , H03F2200/78
摘要： PROBLEM TO BE SOLVED: To provide an optical communication module including a transimpedance amplifier which implements a high speed and high quality receiving operation.SOLUTION: A transimpedance amplifier TIA includes: a preamplifier PRAMP for converting an input single phase current signal to a single phase voltage signal; a threshold detection circuit ATC for detecting a center potential of the single phase voltage signal output from the preamplifier PRAMP; a post amplifier PSAMP for differentiating and amplifying the single phase voltage signal output from the preamplifier PRAMP; and a power circuit PSPY for supplying power to the preamplifier PRAMP. In particular, the power circuit PSPY outputs a change current flowing to a power terminal of the preamplifier PRAMP and a change current having the opposite phase to the change current in accordance with an input voltage signal or output voltage signal of the preamplifier PRAMP. This cancels a supply current change.
摘要翻译：要解决的问题：提供一种包括实现高速和高质量接收操作的跨阻放大器的光通信模块。解阻抗：跨阻放大器TIA包括：前置放大器PRAMP，用于将输入单相电流信号转换为单相电压信号; 阈值检测电路ATC，用于检测从前置放大器PRAMP输出的单相电压信号的中心电位; 后置放大器PSAMP，用于对从前置放大器PRAMP输出的单相电压信号进行微分和放大; 以及用于向前置放大器PRAMP供电的电源电路PSPY。特别地，电源电路PSPY根据前置放大器PRAMP的输入电压信号或输出电压信号输出流向前置放大器PRAMP的电源端子的变化电流和与变化电流相反的相位的变化电流。这取消了电源电流的变化。版权所有（C）2013，JPO＆INPIT

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