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11. 发明专利

JPH01194444A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01194444A
公开(公告)日：1989-08-04
申请号：JP1980688
申请日：1988-01-29
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , TANAKA TAMOTSU , EMOTO YOSHIAKI , KURODA SHIGEO
IPC分类号： H01L21/60 , H01L27/10
摘要： PURPOSE:To reduce a software error due to an alpha-ray by forming an alpha-ray shielding film on the memory circuit forming region of a semiconductor chip when salient-electrodes are formed by lift-off technique on the peripheral circuit forming region of the chip formed of a memory circuit and a peripheral circuit. CONSTITUTION:An alpha-ray shielding film 22 is formed on a passivation film 21AB in a region of a memory circuit RAM of a semiconductor chip 21 formed of a memory circuit and a peripheral circuit or/and a region of a circuit formed of a complementary MISFET. The film 22 is formed to shield an alpha-ray radiated from a radioactive element (U, Th) generation source containing a small amount mainly on salient-electrodes 8. The film 22 is formed of a polyimide series resin film, such as a polyimide/isoindoloquinazolinedione film. The film 22 is formed on a region except a region formed with the electrode 8. Since the film 22 has different thermal expansion coefficient from that of the semiconductor substrate 21A of the chip 21, the film 22 is not brought into contact with the electrode 8 due to the damage or breakdown of the electrode 8 by a thermal stress.

12. 发明专利

JPS63305530A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63305530A
公开(公告)日：1988-12-13
申请号：JP14202687
申请日：1987-06-05
申请人： HITACHI LTD
发明人： EMOTO YOSHIAKI , TANAKA TAMOTSU , MIYAMOTO HIROAKI , KURODA SHIGEO , OTSUKA KANJI
IPC分类号： H01L21/3205 , H01L21/60
摘要： PURPOSE:To improve the accuracy of patterns for conductive films in a wiring, an electrode, etc., by forming a photosensitive second film onto a first film, exposing and developing the second film to shape a first opening, etching the first film to form a second opening and depositing a metallic film into the first and second openings and forming conductor films. CONSTITUTION:A first film 35 not photosensitized is formed onto a substrate 1, a photosensitive second film 36 is shaped onto the film 35, the second film 36 is exposed and developed to form first openings 37 in specified sections, the first film 35 exposed from the first openings 37 are etched to shape second openings having opening diameters larger than those of the first openings 37, and metallic films 25 are deposited into the first openings 37 and the second openings and conductor films are formed. Accordingly, developing patterns are not broken by irregular reflection from wirings, electrodes, etc., thus improving the accuracy of patterns for the conductive films in the wirings, the electrodes, etc.

13. 发明专利

JPS63266861A REPAIR OF CHIP 失效
公开(公告)号：JPS63266861A
公开(公告)日：1988-11-02
申请号：JP9979287
申请日：1987-04-24
申请人： HITACHI LTD
发明人： SATO MASAYUKI , TANAKA TAMOTSU
IPC分类号： H01L23/50 , H01L21/60
摘要： PURPOSE:To enhance the reliability by suppressing the irregularity of a content of Sn by a method wherein a carrier sheet is mounted by being sandwiched between an LSI chip and a substrate, microscopic parts at parts to be connected by a solder are melted and fixed and the irregularity of the volume of solder bumps is reduced to a minimum so that a height at connected parts can be made uniform. CONSTITUTION:A carrier sheet C is placed on solder bumps 16 for connection use formed on solder base metals 15 of a multilayer wiring substrate 14; an LSI chip 10 is laid face down; solder bumps 12 for connection use are brought into contact with electrodes 9 of the carrier sheet. If an electric current flow therethrough, a tantalum sheet 1 acts as a resistor and generates the heat; a microscopic solder coming into contact with the solder bumps 12, 16 for connection use and the electrodes 9 of the carrier sheet is melted; a switch 17 is turned off; solder bonding parts 13 are fixed. If the characteristics of an LSI chip are defective, the electric current flows through the carrier sheet C again; the LSI chip is detached; a new chip is repaired.

14. 发明专利

JPS6381951A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6381951A
公开(公告)日：1988-04-12
申请号：JP22598186
申请日：1986-09-26
申请人： HITACHI LTD
发明人： OKUYA KEN , OTSUKA KANJI , TANAKA TAMOTSU , SATO TOSHIHIKO , KOBAYASHI TSUNEO , KURODA SHIGEO , EMOTO YOSHIAKI
IPC分类号： H01L21/60
摘要： PURPOSE:To form a bump on the whole surface of a semiconductor chip by a method wherein a resist mask is shaped onto the semiconductor chip, solder for the bump is evaporated through the resist mask, the resist mask is removed and wet-back treatment is executed. CONSTITUTION:A resist mask 12 is formed onto a semiconductor chip 1, a metal 13 for a bump is evaporated through the resist mask 12, the resist mask 12 is removed, and solder spherical bumps can be shaped without using a metallic mask and a push plate through wet-back treatment after taking off the resist mask 12, thus forming the bumps on the whole surface of the semiconductor chip. The resist mask 12 with a cross section having a reverse trapezoidal section (a shape that a hole with a trapezoidal section is formed) can be shaped by forming the resist mask 12 through a reverse tapered sectional shape preparation by one-time photosensitive method or two-time photosensitive method, thus increasing the density of the bumps.

15. 发明专利

JPS6352445A SEMICONDUCOTR DEVICE 失效
公开(公告)号：JPS6352445A
公开(公告)日：1988-03-05
申请号：JP19535186
申请日：1986-08-22
申请人： HITACHI LTD
发明人： TANAKA TAMOTSU , SATO TOSHIHIKO , OKUYA KEN
IPC分类号： H01L21/60 , H01L23/34
摘要： PURPOSE: To improve the heat sink characteristics of a semiconductor device by integrating the innermost layer metal layer of an electrode base layer without separating between a heat sink dummy salient electrodes in a plurality of the projected salient electrodes through the electrode base layer made of multilayer metal layers on internal electrode wirings. CONSTITUTION:A Cr layer 6 of the innermost layer is integrated by omitting etching of the layer 6, and internal electrode wirings 4 and a device surface protecting film 5 are laid on the whole surface. A bump 3A of semispherical Sb-Pb is formed on an Au layer 8. Since the layer 6 of the innermost layer is integrated and an electrode base layer 9 formed with the bump 3A is not separated by the film 5, each bump 3A is not electrically separated, but a heat sink dummy bump does not need an electric separation. Thus, the area of the innermost layer (metal layer) is increased to increase the heat transfer area, thereby improving the heat sink property.

16. 发明专利

JPH08162454A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08162454A
公开(公告)日：1996-06-21
申请号：JP29940494
申请日：1994-12-02
申请人： HITACHI LTD
发明人： IMASU SEISHI , TANAKA TAMOTSU
IPC分类号： H01L23/12 , H01L21/321 , H01L21/60
摘要： PURPOSE: To avoid defective contact of bump electrodes due to the stress such as temperature change etc. CONSTITUTION: A protruded electrode pattern 3b is provided at the electrode 3a of a semiconductor chip 3 electrically connected to a CCB bump 4 and then a gradient with a specific angle in the thickness direction is made on the periphery of the electrode 3a. Next, stress is dispersed by said protrusion and gradient to make the cracking in the CCB 4 hardly occur and stop the crack starts to grow.

17. 发明专利

JPH05299525A 失效
公开(公告)号：JPH05299525A
公开(公告)日：1993-11-12
申请号：JP10678492
申请日：1992-04-24
申请人： HITACHI LTD
发明人： NISHIZAWA HIROTAKA , TANAKA TAMOTSU , TOKUDA MASAHIDE , KOBAYASHI TORU
IPC分类号： H01L23/02
摘要： PURPOSE:To enable the cracking of bump electrodes due to the temperature cycle in a sealing part structure to be avoided by a method wherein the sealing part of the title device is hermetically sealed with the anisotropical bellows absorbing or relieving the thermal stress displacement or strain of a semiconductor chip. CONSTITUTION:A semiconductor chip 12 is surface mounted on a base substrate 11 using a hermetically sealing device between this base substrate 11 and a sealing cap 14. At this time, the sealing parts 16, 17 of this device are hermetically sealed with anisotropical bellows 15 absorbing or relieving the thermal stress displacement or strain. Accordingly, the deformation of the bump electrodes 13 on the semiconductor chip 12 thermally expanding and contracting in the longitudinal direction can make the stress balance by the elastic deformation of the anisotropical bellows not only in the thermal equilibrium state but also in the thermal non-equilibrium state. Through these procedures, the cracking of bump electrodes 13 can be avoided.

18. 发明专利

JPH04206562A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04206562A
公开(公告)日：1992-07-28
申请号：JP32939690
申请日：1990-11-30
申请人： HITACHI LTD
发明人： TANAKA TAMOTSU
IPC分类号： H01L23/538
摘要： PURPOSE:To enable a semiconductor device to be improved in yield and easily enhanced in degree of integration by a method wherein a first chip where common elements are formed and a second chip where a wiring layer is formed are previously checked and then electrically connected together through the intermediary of micro-bumps. CONSTITUTION:A first chip 1 is provided with a large number of basic cells 2 of elements formed of single crystal silicon or the like arranged in matrix almost throughout its surface. On the other hand, a second chip 3 is formed of material of the same thermal expansion coefficient with that of the chip 1 and provided with a wiring layer, I/O cells, and I/O pads 5. The chips 1 and 3 are electrically connected together through the intermediary of fine bumps 6 formed of solder, aluminum, gold, silver, or the like. A semiconductor device of this design can be changed in logic by using the chip 3 modified in wiring layout. Chips are previously checked, whereby a semiconductor device can be prevented from decreasing in yield due to a defective wiring layer.

19. 发明专利

JPH01207163A DISCHARGE NOZZLE AND SPIN COATER USING SAID NOZZLE 失效
公开(公告)号：JPH01207163A
公开(公告)日：1989-08-21
申请号：JP3073488
申请日：1988-02-15
申请人： HITACHI LTD
发明人： TANAKA TAMOTSU , MIYAMOTO HIROAKI , EMOTO YOSHIAKI
IPC分类号： B05C5/00 , B05C11/08 , G03F7/16 , H01L21/027 , H01L21/30
摘要： PURPOSE:To stably maintain discharge characteristics such as discharge direction and rate of liquid from a discharge nozzle by gradually increasing the bore of the discharge nozzle in the direction toward an open end, thereby forming the nozzle to a trumpet shape. CONSTITUTION:A turn table is rotated at a prescribed speed and a liquid 8 such as photoresist supplied from the discharge nozzle 3 is sprayed and coated to the central part of a material 2 to be coated uniformly over the entire surface of the material 2, by which the photoresist layer or the like of a prescribed thickness is formed on the surface of the material 2. The trumpet shaped part 3a which is gradually increased in the bore toward the open end side is formed to the front end of the discharge nozzle 3. The liquid 8 which has a partially spherically shape crowning to a lower side is drawn into the discharge nozzle and does not stick at all to the front end of the discharge nozzle 3. Remaining of the liquid 8 at the front end of the discharge nozzle 3 after repetition of discharging and suck-back operations and the irregular growth of the liquid by drying and solidifying of said liquid are thus surely prevented. As a result, the discharge characteristics such as the discharge direction and rate of the liquid 8 to the material 2 to be coated are stabilized.

20. 发明专利

JPH01194450A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01194450A
公开(公告)日：1989-08-04
申请号：JP1980788
申请日：1988-01-29
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , EMOTO YOSHIAKI , TANAKA TAMOTSU , KURODA SHIGEO
IPC分类号： H01L23/522 , H01L21/60 , H01L21/768 , H01L23/52
摘要： PURPOSE:To form wirings of small size by forming a second resist film on a whole circuit substrate including a first resist film disposed on the circuit substrate and a wiring forming region, and forming wirings mainly made of Cu in an accuracy corresponding to the working size of the first opening of the second resist film. CONSTITUTION:In a region not formed with wirings 23C, an interlayer insulating film 23B is disposed on a circuit substrate 23A to form a first resist film 18. Then, second resist films 19 are formed on the region formed with the wirings 23C and the film 18 of the region not formed with the wirings 23C. A first opening (groove) 20A is formed on the film 19 of the region formed with the wirings 23C, and a second opening 20B is formed at the film 19 of the region not formed with the wirings 23C. Then, a metal film 23E mainly formed of Cu is deposited on the whole substrate 23A, the films 19, 18 are then removed, the wirings 23C in the opening 20A remain, and dummy wirings 23D on the film 18 and the metal film 23E on the film 19 are removed.

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