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11. 发明专利

JPS6352257A MICROPROCESSOR 失效
公开(公告)号：JPS6352257A
公开(公告)日：1988-03-05
申请号：JP19530586
申请日：1986-08-22
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO
IPC分类号： G06F13/28
摘要： PURPOSE:To process a device having high priority at a high speed by securing such constitution where a microprocessor completes immediately its executing bus cycle and clears a bus master with a bus request given from a device of high priority. CONSTITUTION:A direct memory access controller DMAC sets a signal of a terminal R and R at a low level, i.e., in an active state when data having a high degree of emergency is transferred and at the same time delivers a bus request signal. A microprocessor MPU is set in a halt state as soon as a machine cycle synchronous with a clock E is finished after the signal of the terminal R and R is set at a low level. Then an address terminal and a data terminal are set at high impedance and a bus acknowledge signal is also delivered from the MPU. Thus the DMAC acquires a bus and transmits a signal showing a busy mode of the bus to other devices. Then the DMAC gives access to a memory device RAM as well as floppy memory devices FDC and FDD for execution of transfer of data among them.

12. 发明专利

JPH03150594A SYSTEM AND DEVICE FOR CHARACTER GENERATION AND DOCUMENT PRINTER 失效
公开(公告)号：JPH03150594A
公开(公告)日：1991-06-26
申请号：JP29042289
申请日：1989-11-08
申请人： HITACHI LTD
发明人： HASEGAWA KAZUKO , SUZUKI YOSHITO , KAWABATA HISAYOSHI , NAKAMURA NAOKI , HORIUCHI YUICHI
IPC分类号： G09G5/26 , G09G5/24
摘要： PURPOSE:To output characters of high quality even in character zooming in consideration of the characteristics of an output device by obtaining raster type character data from contour coordinate data form reducing characters in thickness almost one picture element of the output device according to contour coordinate data on characters after conversion. CONSTITUTION:The contour coordinate data on a character which is transferred from a font ROM 2 is received and an affine conversion part 42 performs character shape deformation such as enlargement or reduction according to modification information on the character. The coordinate data obtained by the shape conversion is further coordinate-converted by a coordinate movement part 43 so as to make the character thin, and then stored in an internal data RAM 44 temporarily. A contour generation part 46 generates dot information indicating the contour on an internal RAM 48 according to the data stored in the internal data RAM 44. Further, a painting-out data generation part 47 generates painting-out data according to the information in the internal RAM 48 and transfers this data to the output device 5 to output the character. Consequently, the character with thickness corresponding to the characteristics of the specific output device can be outputted and the character quality is improved.

13. 发明专利

JPS62114055A DIRECT MEMORY ACCESS CONTROL DEVICE 失效
公开(公告)号：JPS62114055A
公开(公告)日：1987-05-25
申请号：JP25273485
申请日：1985-11-13
申请人： HITACHI LTD
发明人： TSUNEHIRO TAKASHI , KUBOTA KAZUMI , SUZUKI YOSHITO
IPC分类号： G06F13/28
摘要： PURPOSE:To execute a data transfer at high speed when a data is transferred from a memory to memory by a DMA transfer system, by providing each separate address register for read-out and write, and switching and operating both of them. CONSTITUTION:A selecting port 15 is provided in order to inform to a distributor 16 whether a memory to which an access is executed at present is in a read-out side or a write side, and in accordance with the output of this port 15, the distributor 16 distributes the output of a clock port 12 and the output of an enable port 13 to the first address register 17 and the second address register 18. At the time of read-out, the higher rank of an address is set to the register 17, and at the time of write, the higher rank of the address is set to the register 18. Such setting of the higher rank of the respective address to the registers 17, 18 is executed only at the time of a data transfer of the first time, and at the second time and thereafter, the setting is executed only when the higher rank address is changed.

14. 发明专利

JPH03225394A CHARACTER GENERATION DEVICE 失效
公开(公告)号：JPH03225394A
公开(公告)日：1991-10-04
申请号：JP1905290
申请日：1990-01-31
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SUZUKI YOSHITO , WAKIZAKA SHINJI , WADA HIROSHI , KOIZUMI HIROYUKI , KANEKO SUSUMU , TAKAHASHI FUMIHIRO , ASAI TOSHIO
IPC分类号： B41J2/485 , G06T3/40 , G06T5/30 , G06T11/20 , G09G5/24 , G09G5/26
摘要： PURPOSE:To correct a line width at a high speed on a small circuit scale which can be formed to an LSI by correcting the width of a specified line to the specified line width while performing coorinate transformation or curve interpolation by affine transformation. CONSTITUTION:The data of coordinate is temporarily stored in a font input FiFo 15 in a host interface 23. An affine transformation block/line width correc tion block 16 orderly reads the data of coordinate (x, y) from the FiFo 15 so as to execute the affine transformation, x'=ax+by+e, Y'=cx+dy+f, pro vided that a-d are the constants of affine matrix data and (e) and (f) are constants. Furthermore, the correction is performed to the data of coordinate (x', Y') in order to correct the line width, and the corrected data (x'', y'') is outputted to an FiFo 20. A line width interpolation block 17 reads the data of coordinate (x', y') or (x'', y''), generates the data of coordinate expressing a curve and outputs it to an FiFo 21. A line generation block 18 generates the contour of a character based on the data of coordinate and writes it in a dot memory 22. A painting-out Bit BLT block 19 paints out the inside of the contour and writes it in a page memory.

15. 发明专利

JPH03138696A CHARACTER DATA STORAGE DEVICE 失效
公开(公告)号：JPH03138696A
公开(公告)日：1991-06-13
申请号：JP27581289
申请日：1989-10-25
申请人： HITACHI LTD
发明人： HASEGAWA KAZUKO , SUZUKI YOSHITO
IPC分类号： B41J2/485 , G09G3/04 , G09G3/20 , G09G5/22
摘要： PURPOSE:To compress character data so as to decrease data capacity and to decrease the burden of a CPU by taking out assigned compressed character data from a means which compresses and stores character data and extending the taken-out compressed character data. CONSTITUTION:Since the compressed character data is stored, the relatively smaller character data capacity is necessitated. Since a compressed character data extending means 13 is provided, the CPU 1 can be inputted with the vector character data by a character code address and a scan address apparently in the same manner as in the case of the conventional dot character ROM. Further, a means 14 for converting the data structure of the character data is provided and, therefore, if the character data is outline character data, the conversion of the data structure is executed to comply with the input data structure of a character generator 3 even if the data structure of the character data after the extension and the input data structure of the character generator 3 are not the same. The burden of the CPU 1 is decreased in this way.

16. 发明专利

JPH02196296A CHARACTER GENERATOR 失效
公开(公告)号：JPH02196296A
公开(公告)日：1990-08-02
申请号：JP1684389
申请日：1989-01-26
申请人： HITACHI LTD
发明人： TANAKA NORIO , HASEGAWA KAZUKO , SUZUKI YOSHITO
IPC分类号： G09G5/26 , G06F3/14
摘要： PURPOSE:To generate various character fonts with small storage capacity by providing the character generator itself with a conversion processing circuit for conversion from outline character data to dot character data. CONSTITUTION:The size of a character font and modes of a qualifying function for inclined characters and void characters, the selection of a character kind, etc., are set in a control register 3 through a data bus 1 from a CPU. A character data memory 5 is stored with outline font data on the original form of characters. The character conversion processing circuit 4 reads character data corresponding to a character code specified through the address bus 2 of the CPU out of the memory 5, processes the character data according to the setting contents of the control register 3 to convert the data into dot font data, and outputs the dot font data corresponding to a raster address onto a dot data bus 6. Consequently, various character fonts can be generated with the small storage capacity.

17. 发明专利

JPS62197994A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62197994A
公开(公告)日：1987-09-01
申请号：JP3918486
申请日：1986-02-26
申请人： HITACHI LTD
发明人： YAMAGA KIYOHISA , IKEDA SHINICHI , SUZUKI YOSHITO
IPC分类号： G11C17/18 , G11C17/00
摘要： PURPOSE:To drive a word line to a selection level at high speed by providing sense amplifiers which drive the word line to the selection level when the level of the word line arrives at a prescribed intermediate level between a non- selection level and the selection level. CONSTITUTION:In a sense amplifier SA1 provided at respective word line terminal at the opposite side of a decoder circuit DCE, a detecting MOSFET Q13 has the intermediate level of the word line between the selection level and the non-selection level, as a threshold voltage. Therefore, by supplying a driving signal from the decoder circuit to a prescribed word line, the MOSFET Q13 is turned on by the slight rising of the level in the word line. Thereby, high level voltage as a good selection level for the word line is supplied from the opposite direction of the propagating direction of the driving signal from the decoder circuit. In this way, the word line can be driven to the selection level at high speed.

18. 发明专利

JPS62123827A OUTPUT CIRCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS62123827A
公开(公告)日：1987-06-05
申请号：JP26242785
申请日：1985-11-25
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO , IKEDA SHINICHI
IPC分类号： H03K19/0175 , H03K17/16 , H03K17/687 , H03K19/003
摘要： PURPOSE:To reduce noise on a ground line by connecting a couple of switch MOSFETs smaller in size than that of each component constituting an output buffer is parallel with each component, and driving the said switch MOSFETs before the drive of the output buffer so as to flow a current gradually to a load. CONSTITUTION:The output terminal of the output buffer 1 is connected in parallel with the output terminal of the switch comprising MOSFETs M1-M4. A signal TSCE driving a switch 10 is supplied before the inverse of signal TSC driving the output buffer 1 is supplies so as to switch the switch 10 by using the same signal being the inverse of signal IN fed to the output buffer 1. Since the size of each component of the switch 10 is constituted small sufficiently, the current is small. Thus, after a load CL is charged or discharged, the inverse of signal TSC is fed to the output buffer 1 to get a driven state. Thus, pulse noise is reduced.

19. 发明专利

JPS61148563A DATA TRANSFER SYSTEM AND DATA TRANSFER 失效
公开(公告)号：JPS61148563A
公开(公告)日：1986-07-07
申请号：JP27081384
申请日：1984-12-24
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO
IPC分类号： G06F13/28 , G06F13/38 , G06T3/60
摘要： PURPOSE:To make a DMA controller highly functional by transferring a series of data groups, which are held in a certain address space with offsets, to another address space with offsets. CONSTITUTION:Transfer information of a memory start address A, a device start address B, a memory-side offset value X, a device-side offset value Y, a number (n) of transfer words, etc. are registered in a table, and the start address and the number of transfer blocks of this table are set to registers BAR and BTC by an MPU. The DMA controller refers to the table indicated by the address set to the register BAR to read start addresses A and B, offset values X and Y, and the number (n) of transfer words of the first block into registers marked with *, and thereafter block transfer is started.

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