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1. 发明专利

JPH04205852A DISK CACHE DEVICE 失效
公开(公告)号：JPH04205852A
公开(公告)日：1992-07-28
申请号：JP32884490
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YAMAZAKI YUKIE , SHIMADA YUJI , HOCCHI YASUO , SUZUKI YOSHITO
IPC分类号： G06F12/08 , G06F1/32 , G11B19/00
摘要： PURPOSE:To achieve a low power consumption by a method wherein, only at an erroneous hitting operation, a spindle motor for a magnetic disk is sctuated and wasteful consumption of electric power is reduced. CONSTITUTION:When a processing operation is started, a disk cache memory controller 203 turns off a spindle motor 211 by using a power-saving control 2. Together with this, a power supply for a signal processing circuit is turned off by using a power-saving control 1. Until a request comes from a host computer, the disk cache memory controller 203 is on standby in a low power consumption state. The low power consumption state refers to a state that, e.g. a clock which is input to the disk cache memory controller 203 is stopped so as to restrain wasteful consumption of electric power. Thereby, the low power consumption of the title device can be achieved.

2. 发明专利

JPH04178718A MULTIPLE MAGNETIC DISK DEVICE AND COMPOUND SYSTEM 失效
公开(公告)号：JPH04178718A
公开(公告)日：1992-06-25
申请号：JP30410790
申请日：1990-11-13
申请人： HITACHI LTD
发明人： HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , SUZUKI YOSHITO
IPC分类号： G06F3/06
摘要： PURPOSE:To decrease the probability that wrong data in missed and data is corrected into wrong data by performing error detection and error correction doubly by means of a host controller and a magnetic disk controller. CONSTITUTION:A small-sized magnetic disk device 41 performs error detection and correction for data by using an error correcting circuit 41a. When no error is detected or after an error is corrected, the data are sent to the host controller 30. Other small-sized magnetic disk devices 42 - 44 also operate similarly. Then the host controller 30 stores buffers 31 - 34 with data sent from the magnetic disk devices 41 - 44 temporarily and while data parts are stored in a buffer 30b, an error correcting circuit 30a performs error detection and error correction like error correcting circuits 41a - 44a perform. Consequently, the probability that wrong data is missed and data is corrected into wrong data is reduced.

3. 发明专利

JPS63153634A DATA PROCESSOR 失效
公开(公告)号：JPS63153634A
公开(公告)日：1988-06-27
申请号：JP29872186
申请日：1986-12-17
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO
IPC分类号： G06F9/30 , G06F1/08 , G06F9/22 , G06F15/78
摘要： PURPOSE:To easily speed up the processing of a processor without argely altering its design large even if some of its internal circuits is slow in operation speed by extending an internal clock signal when a specific instruction is execut ed. CONSTITUTION:When the specific instruction for which the slowest circuit in the processor needs to operate is fetched in an instruction register 1 and a microinstruction for it is read out of a microprogram control part 2, control signals phi1WE and phi2WE are sent from a decoder 3 for control which decodes the microinstruction to a clock generator 5. Therefore, internal clock signals phi1 and phi2 are extended only when the specific instruction is executed, and three cycles of a clock CLK whose one cycle normally corresponds to one machine cycle are regarded as one machine cycle, so that the instruction is executed. Consequently, the frequency of a reference clock can be increased as much as possible according to the speed of circuits except the slowest circuit.

4. 发明专利

JPS613247A LOGICAL LSI 失效
公开(公告)号：JPS613247A
公开(公告)日：1986-01-09
申请号：JP12175384
申请日：1984-06-15
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO
IPC分类号： G06F9/22 , G06F9/26 , G06F15/78
摘要： PURPOSE:To facilitate the logical design of a logical part including order control by providing plural microprogram sequencers and microprogram memories on the same chip and thus constituting the logical LSI. CONSTITUTION:When the 1st entry input is supplied to an address generation part PLA, transfer gates G1-G8 are opened to generate the 1st microprogram address, which is sent to a decoder DEC to read out a microinstruction, thereby outputting various control signals and a next address. The transfer gates G1- G8 are turned off and G11-G18 are turned off with some of the control signals. Conseqently, the next address is supplied to the decoder DEC to read a next microinstruction out. Thus, a series of microinstructions are read out and supplied to respective parts of logical circuits constituting a system outside the chip from an output terminal DO, thereby performing sequential control.

5. 发明专利

JPS6015945A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6015945A
公开(公告)日：1985-01-26
申请号：JP12321683
申请日：1983-07-08
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO
IPC分类号： H01L27/112 , H01L21/82 , H01L21/8246 , H01L27/10
摘要： PURPOSE:To enable to vary a function arbitrarily by providing a MOS array containing a MOSFET for memory, to an input line thereof a gate is connected, to an output line thereof one electrode is connected and to the other electrode thereof high-level or low-level potential formed by a memory means is fed. CONSTITUTION:Program language from an instruction register 1 is inputted to a register 3 through a gate 2. A series of control pulses phi formed by a pulse generating circuit are transmitted over a decoding tree 4. Each pulse passes through one output line from the decoding tree 4 according to instruction words from the register 3, and is inputted to a control matrix 5. A select control matrix 5a operates various gates in a static control field 6 by its output. An order control matrix 5b outputs an address for the next micro-instruction to be executed to a register 7. When a micro-instruction consisting of one or several steps to one program word from the instruction register 1 is executed completely, the gate 2 is opened, and the next program word is taken in.

6. 发明专利

JPS59107634A Output circuit in mos integrated circuit 失效
标题翻译： MOS集成电路中的输出电路
公开(公告)号：JPS59107634A
公开(公告)日：1984-06-21
申请号：JP21692282
申请日：1982-12-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： SUZUKI YOSHITO , SHINAGAWA YUTAKA
IPC分类号： H03K19/0944 , H03K17/687 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： PURPOSE:To increase the electrostatic breakdown strength of an output pin by constituting the circuit that a depletion type MOSFET is connected between the output pin and an output buffer to make a high voltage applicable to its gate. CONSTITUTION:MOSFETQ1, Q2 constituting an output stage 3a are turned on/ off complementarily. Further, a depletion MOSFETQ3 is connected between an output pad 5 and an output node n1 of the output buffer circuit 3. A gate terminal of the FETQ3 is connected to a power supply line and a power supply voltage VDD is applied thereto. When the FETQ3 is used in an LSI and a power supply voltage is applied to a power supply pin, the gate voltage is brought to a level of the voltage VDD and its resistance value is suppressed to a low value. Further, when no power supply voltage is applied to the LSI in the operation such as handling or the like, the gate voltage is brought to 0V and the resistance value of the FETQ3 is increased. As a result, the speed of the output circuit 3 at the operation as the LSI is reduced slightly and electrostatic breakdown is prevented at handling.
摘要翻译：目的：通过构成在输出引脚和输出缓冲器之间连接耗尽型MOSFET的电路来提高输出引脚的静电击穿强度，以使其栅极具有高电压。构成：构成输出级3a的MOSFETQ1，Q2互补地开/关。此外，耗尽MOSFETQ3连接在输出缓冲电路3的输出焊盘5和输出节点n1之间.FETQ3的栅极端子连接到电源线，并且向其施加电源电压VDD。当在LSI中使用FETQ3并且将电源电压施加到电源引脚时，栅极电压达到电压VDD的电平，并且其电阻值被抑制到低值。此外，当在诸如处理等的操作中没有向LSI施加电源电压时，栅极电压变为0V并且FETQ3的电阻值增加。结果，输出电路3在作为LSI的操作时的速度稍微减小，并且在处理时防止静电击穿。

7. 发明专利

JPH03214368A PAINTING-OUT CIRCUIT 失效
公开(公告)号：JPH03214368A
公开(公告)日：1991-09-19
申请号：JP999390
申请日：1990-01-19
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SUZUKI YOSHITO , YANAGIDA HIRONOBU
IPC分类号： G09G5/36 , G06T11/40
摘要： PURPOSE:To prevent the painting-out start point from being inverted at the time of painting-out processing of variation point data by providing an OR term of the corresponding input as an output of a combining circuit. CONSTITUTION:When inputs I1 - In are supplied to a combining circuit 101 in accordance with variation point data of a first word of (n) bits, in accordance with logic of the combining circuit 101, for instance, outputs O2 - On corresponding to the input I2 of logic 1 corresponding to a start point of painting-out are outputted as logic 1. Each output O1 - On has an exclusive OR term to the respective inputs of the lower side than the corresponding input. Accordingly, a result of its exclusive OR term is set to logic '0' until immediately before the exclusive logical operation term for receiving the input I2 (a painting-out start point of logic 1), and a result of the exclusive OR term responding to the upper input I3 that the input maintains logic 1 until the input becomes logic 1 which signifies the painting-out end point. In such a way, the part between the start point and the end point of painting-out is painted out, and when plural start points and end points exist, the bit between them is not painted out.

8. 发明专利

JPS6079819A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6079819A
公开(公告)日：1985-05-07
申请号：JP18676683
申请日：1983-10-07
申请人： HITACHI LTD
发明人： SUZUKI YOSHITO , YAMAGA KIYOHISA
IPC分类号： H03K19/0948 , H03K17/687 , H03K19/0944 , H03K19/096
摘要： PURPOSE:To obtain a gate circuit for transmitting a signal stably by providing the 1st and 2nd transfer gate MOSFETs, an MOSFET operated complementarily to the former FETs and an inverter circuit. CONSTITUTION:A transmission gate MOSFETQ1 for transmitting a clock signal phi which is a signal to be transmitted is provided between an input terminal IN and an output terminal OUT. A control signal (enable signal) E is fed to the gate of the Q1 via a transmission gate MOSFETQ2. The clock signal phi being a signal to be transmitted and fed to the input terminal IN is inverted by an inverter circuit IV2 and fed to the gate of the said Q2. Furthermore, an MOSFET3 receiving the control signal E inverted by the inverter circuit IV1 is provided between the output terminal OUT and a ground potential of the circuit.

9. 发明专利

JPH0511733A CHARACTER GENERATING DEVICE 失效
公开(公告)号：JPH0511733A
公开(公告)日：1993-01-22
申请号：JP891991
申请日：1991-01-29
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKI YOSHITO , WAKIZAKA SHINJI , WADA HIROSHI , KOIZUMI HIROYUKI , KANEKO SUSUMU , TAKAHASHI FUMIHIRO , ASAI TOSHIO
IPC分类号： G06F3/153 , G06T3/40 , G06T5/30 , G06T11/20 , G09G5/24
摘要： PURPOSE:To reduce memory as well as to shorten processing time to facilitate LSI formation by making line width compensation simultaneously with affine transformation or curve interpolation. CONSTITUTION:While character font data 1 of a vector form are transformed coordinately or curve-interpolated in a control part 2 for line width compensation by affine transformation as well as the coordinate transformations such as affine transformation, curve interpolation, etc., the line width of a specified linear line is compensated to a specified line width. Then a flag data showing the content of compensation is added to the coordinate data to be modified. It is desirable to compensate the line width by modifying the coordinate data according to the flag data. Also it is desirable to modify the line width in vertical direction only relative to the vector facing toward the coordinate data to be processed next.

10. 发明专利

JPH0437793A CHARACTER GENERATING DEVICE 失效
公开(公告)号：JPH0437793A
公开(公告)日：1992-02-07
申请号：JP14462290
申请日：1990-06-01
申请人： HITACHI LTD
发明人： HASEGAWA KAZUKO , TANAKA NORIO , WAKIZAKA SHINJI , SUZUKI YOSHITO
IPC分类号： G09G5/22 , G06T11/20
摘要： PURPOSE:To increase the character output speed by providing three buses, i.e. a control data bus which inputs control data, a font bus which inputs font data, and an output data bus which outputs bit map data to the character generating device which inputs the font data on characters and converts them into bit map data. CONSTITUTION:A CPU 1 actuates the character generating device 3 and transfers character code data on characters to be outputted to the character generating device 3 through the control data bus 7. The character generating device 3 which receives the character code data inputs font data such as contour information, etc., on the corresponding characters from a font ROM 2 through the font data bus 8 according to the character code data. The character generating device 3 converts the font data inputted from the font ROM 2 into the bit map data according to various kinds of information inputted from an input device 6 and outputs them. The bit map data outputted from the character generating device 3 are transferred to a memory 4 through the output data bus 9 and the contents of the memory 4 are outputted to an output engine 5 to print or display the characters.

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