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11. 发明专利

JP2008112485A Synchronous memory circuit 有权
标题翻译：同步存储器电路（SYNCHRONOUS MEMORY CIRCUIT）
公开(公告)号：JP2008112485A
公开(公告)日：2008-05-15
申请号：JP2006293486
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HASEGAWA MASATOSHI , NAKAYAMA MICHIAKI , SAKAMOTO MASATOSHI
IPC分类号： G11C11/417 , G11C11/407
CPC分类号： G11C8/12 , G11C7/1012 , G11C7/1027 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a memory circuit achieving both high access efficiency and memory efficiency with a simple configuration.
SOLUTION: In a memory read control circuit, a burst length is changed according to whether a read instruction is given to the following cycle to which a read instruction/R is given. Also in a write control circuit, the burst length is changed according to whether a write instruction is given to a cycle before a write instruction/W is given.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备有通过简单配置实现高访问效率和存储器效率的存储电路的半导体集成电路器件。解决方案：在存储器读取控制电路中，突发长度根据读取指令是否被给予读取指令/ R的后续周期而改变。另外，在写入控制电路中，突发长度根据在给出写入指令/ W之前是否向周期给出写入指令而改变。版权所有（C）2008，JPO＆INPIT

12. 发明专利

JP2007080283A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2007080283A
公开(公告)日：2007-03-29
申请号：JP2006293469
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/00 , G06F12/08 , G11C11/406
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which easily accepts a write access request regardless of an internal memory operational status. SOLUTION: A semiconductor integrated circuit (1) includes a plurality of memory banks (BNK0-BNK7) formed on a semiconductor chip (1A), a plurality of write buffers (WB0-WB3), an external input circuit (I/F1) and a control circuit (MCNT). Each of the plurality of memory banks includes a data input part and a plurality of memory cells periodically requiring stored data refreshing operations. The control circuit controls a corresponding write buffer so as to selectively hold data supplied to the external input circuit in the corresponding write buffer during a period of time for the refresh operation and the read operation of a corresponding memory bank, and control the corresponding write buffer to supply data to the corresponding memory bank after the completion of the refresh operation and the read operation of the corresponding memory bank. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种容易接受写访问请求的半导体集成电路，而不管内部存储器操作状态如何。解决方案：半导体集成电路（1）包括形成在半导体芯片（1A）上的多个存储体（BNK0-BNK7），多个写入缓冲器（WB0-WB3），外部输入电路（I / F1）和控制电路（MCNT）。多个存储体中的每一个都包括周期性地要求存储的数据刷新操作的数据输入部分和多个存储器单元。控制电路控制相应的写入缓冲器，以便在对应的存储体的刷新操作和读取操作的时间段期间选择性地保持提供给相应写缓冲器中的外部输入电路的数据，并且控制对应的写入缓冲器在完成刷新操作和对应的存储体的读取操作之后向对应的存储体提供数据。版权所有（C）2007，JPO＆INPIT

13. 发明专利

JP2001091590A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001091590A
公开(公告)日：2001-04-06
申请号：JP26676799
申请日：1999-09-21
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KURITA KOZABURO
IPC分类号： G06F11/22 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a technology for detecting the incorrect delay of a logic block without causing a significant increase of product cost. SOLUTION: A self diagnostic circuit comprises a first circuit 601 generating a clock signal for performing scanning operation through a scan path at a rate lower than the actual working rate of a diagnostic block, and a second circuit 602 generating a clock signal for performing supply of pseudo-random numbers to a logic block and collection of output signals therefrom at a rate substantially equal to the actual working rate of the logic block. Consequently, the incorrect delay of the logic block can be detected without reducing the line resistance by enlarging the line width or providing an amplifier in the scan path.

14. 发明专利

JPH11102910A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11102910A
公开(公告)日：1999-04-13
申请号：JP26306097
申请日：1997-09-29
申请人： HITACHI LTD
发明人： KONO MASAKI , NAKAYAMA MICHIAKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To prevent the freedom of signal wirings of a semiconductor integrated circuit from being obstructed on account of power source wirings. SOLUTION: This circuit 1 is provided with a retaining substrate 2, a first wiring layer 3 which is formed on the retaining substrate 2 and on which a plurality of first wirings are formed, a circuit element forming layer 4 formed on the first wiring layer 3, and a second wiring layer 5 which is formed on the circuit element forming layer 4 and has a plurality of second and third wirings which are connected with circuit elements of the circuit element forming layer 4. The first wirings are made power source wirings 31, 32, the second wirings are made signal wirings 53a, 53b, 53c, and the third wirings are made power source wirings 52a, 52b. Power source main lines can be constituted of the first wirings of the first wiring layer 3, arrangement of the power source main lines on the second wiring layer 5 is unnecessary, and the third wirings can be comparatively short.

15. 发明专利

JPH10242397A CMOS INTEGRATED CIRCUIT DEVICE AND TESTING METHOD 失效
公开(公告)号：JPH10242397A
公开(公告)日：1998-09-11
申请号：JP5554597
申请日：1997-02-24
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , NAKAYAMA MICHIAKI
IPC分类号： G01R31/26 , G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a CMOS integrated circuit and a testing method that allow an accurate DC leakage current test with a simple configuration and achieve a stable operation. SOLUTION: A CMOS integrated circuit is divided into a plurality of circuit blocks, a power supply line 5 and a power supply terminal 4 are provided corresponding to them, at the same time a MOS switch for connecting the above power supply lines between the above adjacent circuit blocks 18 and a control circuit for performing the switch control are provided, and the above MOS switch is turned off by the above control circuit in a DC testing mode and the current supply line 5 of the specific circuit block 8 is separated from the power supply line 5 of another circuit block 18 being adjacent to it.

16. 发明专利

JPH03176892A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03176892A
公开(公告)日：1991-07-31
申请号：JP31466589
申请日：1989-12-04
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , MIYAOKA SHUICHI , MIYAMOTO KAZUHISA , ODAKA MASANORI
IPC分类号： G11C11/41 , G11C11/401
摘要： PURPOSE:To accelerate an operation by arranging a latch circuit, an X/Y decoder circuit in an area between a logic circuit and a memory cell array part from a logic circuit side. CONSTITUTION:An input/output circuit 2 is arranged in the peripheral part of a semiconductor substrate 1, and the logic circuit 3 is arranged in the center part in the upward/downward direction of the semiconductor substrate 1. And the latch circuit 7, the X/Y decoder circuit 8 are arranged in the area between the logic circuit 3 and the memory cell array part 5 from the logic circuit 3 side, respectively. Therefore, since distance between the latch circuit 7 and the X decoder 8 can be reduced, wiring length between them can be reduced, which reduces the transmission delay of a signal on the wiring of the address signal of an X system. In such a way, the operation can be accelerated.

17. 发明专利

JP2009021387A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009021387A
公开(公告)日：2009-01-29
申请号：JP2007182746
申请日：2007-07-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KONO MASAKI , NAKAYAMA MICHIAKI
IPC分类号： H01L21/822 , G06F1/10 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To solve the problem that the timing displacement of signals is generated by a surrounding environment, the change of a power supply voltage by noise or the like or the change of the ambient temperature of a semiconductor device (including the temperature of the semiconductor device itself) for instance, even when timing is adjusted when supplying power and signals can not be normally transmitted since a timing width in which data can be normally fetched is reduced as a signal transmission speed becomes high. SOLUTION: A displacement amount detection circuit part 7 is newly provided inside an LSI 1, a circuit inside the displacement detection circuit part outputs a displacement amount dynamically changing after power supply, and a timing control circuit adjusts the timing again on the basis of the outputted change amount. Thus, even when the timing is displaced, the signals are normally transmitted. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了解决周围环境产生信号的定时位移的问题，电源电压由噪声等的变化或半导体器件的环境温度的变化（包括半导体器件本身的温度），即使在供电时调整定时，也不能正常发送信号，因为可以正常取出数据的定时宽度随着信号传输速度变高而降低。解决方案：在LSI1内部新设置位移量检测电路部7，位移检测电路部内的电路输出电源后动态变化的位移量，定时控制电路基于的输出变化量。因此，即使当定时被移位时，信号也被正常传输。版权所有（C）2009，JPO＆INPIT

18. 发明专利

JP2009015964A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2009015964A
公开(公告)日：2009-01-22
申请号：JP2007176864
申请日：2007-07-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAMOTO MASATOSHI , HASEGAWA MASATOSHI , NAKAYAMA MICHIAKI
IPC分类号： G11C29/02 , G11C11/417 , H01L21/822 , H01L27/04 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, of which the adjustment of input/output timing on various test patterns is possible. SOLUTION: The test pattern of an LSI for control is stored in a memory LSI as expected value data, and when the input/output timing is adjusted, the device is coped with all of the test patterns in a common discrimination circuit by means of discriminating with comparison of expected value data in the memory LSI and input data. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路器件，其中可以在各种测试图案上调整输入/输出定时。解决方案：用于控制的LSI的测试图案作为预期值数据存储在存储器LSI中，并且当调节输入/输出定时时，该设备通过共同鉴别电路处理所有测试图案与存储器LSI中的期望值数据和输入数据的比较来区分的手段。版权所有（C）2009，JPO＆INPIT

19. 发明专利

JP2004006868A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：JP2004006868A
公开(公告)日：2004-01-08
申请号：JP2003133988
申请日：2003-05-13
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , HAMAMOTO MASATO , MORI KAZUTAKA , ISOMURA SATORU
IPC分类号： G01R31/28 , H01L21/822 , H01L21/8238 , H01L21/8244 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To improve layout efficiency of a semiconductor integrated circuit device. SOLUTION: An n-type well 2 on which one transistor Tp constituting a CMOS circuit is arranged, and a supply voltage line Vdd, are electrically connected through a transistor Tps for switching. A p-type well 3 on which the other transistor Tn constituting a CMOS circuit is arranged, and a supply voltage line Vss, are electrically connected through a transistor Tns for switching. At the time of testing the semiconductor integrated circuit device, the transistors Tps and Tns for switching are turned off, and electric potential suitable for the test is supplied from the outside to the n-type well 2 and the p-type well 3, to inhibit thermal runaway caused by leakage currents. Meanwhile, at the time of the normal operation of the semiconductor integrated circuit device, the transistors Tps and Tns for switching are turned on, and the n-type well 2 and the p-type well 3 are set at the supply voltages Vdd and Vss, to prevent latch up. COPYRIGHT: (C)2004,JPO

20. 发明专利

JP2002299561A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2002299561A
公开(公告)日：2002-10-11
申请号：JP2001099324
申请日：2001-03-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TSUBAKI TAKASHI , KITAMURA NOBUAKI , NAKAYAMA MICHIAKI , MIYAOKA SHUICHI
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/02 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To confirm correct writing of additional information for enhancing traceability easily and surely in a short time even if the volume of the additional information is increased. SOLUTION: The semiconductor integrated circuit device comprises parity check logic circuits 10a-10d, and fuse circuits 20-27 for writing additional information. The fuse circuits 20-27 are provided at a redundancy fuse repairing section 12 and written, as additional information, with a format code, the start year of wiring, a month code of wiring lot, the wiring lot number, the wiring lot number suffix, the wafer number, the chip address, and the trimming information. A parity bit is written in the least significant bit of the additional information and, at the time of shipment, the parity check logic circuits 10a-10d perform parity check of the additional information and only a semiconductor integrated circuit device 1 written with correct additional information is shipped.

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