专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JPH10177520A DATA PROCESSOR AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH10177520A
公开(公告)日：1998-06-30
申请号：JP28020797
申请日：1997-10-14
申请人： HITACHI LTD
发明人： NISHIMOTO JUNICHI , NISHII OSAMU , ARAKAWA FUMIO , NARITA SUSUMU , ITO MASAYUKI , TODA MAKOTO , UCHIYAMA KUNIO
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10
摘要： PROBLEM TO BE SOLVED: To provide a data processor which is improved in address converting speed. SOLUTION: The address translation buffer of this data processor is divided into an address translation buffer 4 for data and an address translation buffer 3 for instruction so that address translation information for instruction can also be stored in the buffer 4 and, when a translation error occurs in the buffer 3, new address translation information can be fetched from the buffer 4. The address translating speed of the data processor can be improved as compared with such a case where the address translation information is obtained from an external address translation table whenever a translation error occurs.

12. 发明专利

JPH06348487A MICROPROCESSOR 失效
公开(公告)号：JPH06348487A
公开(公告)日：1994-12-22
申请号：JP16048793
申请日：1993-06-04
申请人： HITACHI LTD
发明人： KAWASAKI IKUYA , NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO
IPC分类号： G06F9/22
摘要： PURPOSE:To reduce the layout area of a chip and to improve operation frequency by arranging an instruction decoder and a micro-ROM so that their signal output terminals are mutually opposed. CONSTITUTION:The output terminals of the instruction decoder 2 and the micro- ROM 3 are arranged so as to be mutually opposed and a selector is connected between both the output terminals. Two input terminals of the selector are arrayed along the output terminal array direction of the decoder 2 and the ROM 3. Thereby the distance of parts causing the increment of areas when the number of signals is large and both the part are separated can be shortened based upon said arrangement relation. In addition, the delay time of a control, signal is suppressed by reducing time constants on output signal transmission lines from the decoder 2 and the ROM 3. An operation execution part 4 is arranged on the side of an selector output to prevent the increment of the whole area.

13. 发明专利

JPH02205109A SCAN LATCH CIRCUIT 失效
公开(公告)号：JPH02205109A
公开(公告)日：1990-08-15
申请号：JP2384189
申请日：1989-02-03
申请人： HITACHI LTD
发明人： ARAKAWA FUMIO , TAKAGI KATSUAKI , IWASAKI KAZUHIKO , KAWASAKI IKUYA
IPC分类号： H03K3/037
摘要： PURPOSE:To prevent waste circuit delay from being generated on an ordinary data path by a scan path by setting a path to scan-in/out by separating from the ordinary path. CONSTITUTION:Ordinary data is inputted to an input terminal D, and is latched at a closed loop formed with a selector 3 and a clock gate 4. Scan data is inputted from a terminal SDin. To latch the value of the terminal SDin at the closed loop, it is necessary to set Sin, C0, and C1 at a low level, a high level, and the low level, respectively. As a result, the value of the SDin is latched at a node 6. The signal level of output F is set at polarity opposite to that applied on the terminal SDin. Therefore, no waste circuit delay is generated on the ordinary path even when an inverter 2 and the selector 3 which form the scan path is added. Thereby, it is possible to perform scan in/out on a part sensitive to the delay time of a critical path, etc.

14. 发明专利

JPS63298077A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63298077A
公开(公告)日：1988-12-05
申请号：JP13114087
申请日：1987-05-29
申请人： HITACHI LTD
发明人： YAMAGUCHI NOBORU , HAGIWARA YOSHIMUNE , HANAWA MAKOTO , ARAKAWA FUMIO , IWASAKI KAZUHIKO
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/0175
摘要： PURPOSE:To reduce an increase in the delay time of an internal signal in normal mode by providing two output driver circuits for internal signal output in a normal operation mode and internal signal output in a test operating mode independently. CONSTITUTION:When a 1-level signal is inputted to a terminal 11 for specifying the test operation mode or normal operation mode, the test operation mode is entered and when a 0-level signal is inputted, the normal operation mode is entered. In the test mode, the internal signal (normal output) which is outputted in the normal operation mode is inhibited from being outputted because tri-state output driver circuits 13 and 14, P-MOS transistors (TR) 134 and 144, and N-MOS TRs 135 and 145 turn off. In this mode, on the other hand, an internal signal (test output) which is outputted in the test mode is outputted to a terminal 15. Similarly, the test signal is inhibited from being outputted in the normal operation mode and the normal output signal is sent out.

15. 发明专利

JPS63286780A FAULT DETECTING SYSTEM AND FAULT DETECTING DEVICE 失效
公开(公告)号：JPS63286780A
公开(公告)日：1988-11-24
申请号：JP12129187
申请日：1987-05-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IWASAKI KAZUHIKO , ARAKAWA FUMIO , MISHINA DAISUKE
IPC分类号： G01R31/317 , G01R31/28
摘要： PURPOSE:To shorten the inspection time, and also, to decrease the hardware by compressing an inspection output pattern of (n) bit width to (m) bits by an exclusive OR network, and thereafter, inputting it to a multi-input feed-back type shift register (MISR). CONSTITUTION:A fault of a logic circuit for compressing an inspection output pattern as a signature is detected by an MISR 3 of (m) bits. That is, an inspection output pattern of (n) (n>m) bit width from a circuit to be inspected 1 such as an LSI, etc. is compressed to (m) bit width by a bit width compressing circuit 2 constituted of an exclusive OR network, and thereafter, inputted to the MISR 3 of (m) bit width. In such a way, a fault can be decided at a high speed without dropping the fault detection rate.

16. 发明专利

JPS63210679A TROUBLE DETECTION CIRCUIT AND TROUBLE DIAGNOSING FOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63210679A
公开(公告)日：1988-09-01
申请号：JP4255587
申请日：1987-02-27
申请人： HITACHI LTD
发明人： IWASAKI KAZUHIKO , KAWASAKI IKUYA , ARAKAWA FUMIO
IPC分类号： G01R31/317 , G01R31/28
摘要： PURPOSE:To enable selection of trouble detection of two symbols or over contained in an input inspection pattern, by providing an exclusive OR circuit between respective stages of a plurality of feedback shift registers. CONSTITUTION:A circuit 1 to be inspected is a logical circuit and (n) results of inspection are outputted per time slot. A signature circuit 2 receives an input of the number (m) of 2-D systems from the circuit 1 being inspected and more than one feedback shift register (MISR), 4, 5, 6,... generate signatures S0, S1, S2,.... A trouble decision circuit 3 receives inputs of the signatures S0, S1, S2,... and judges that trouble is in the circuit 1 being inspected when all the signatures are zero. When one or more signatures are not zero, the circuit 1 being inspected is determined to cause a trouble. Here, the MISRs 4, 5, 6,... have exclusive OR circuits between respective stages thereof with an inspection pattern and outputs of a plurality of other stages or an output of down stage as inputs and detects errors up to (n) symbols.

17. 发明专利

JP2003150371A COMPUTER ELEMENT HAVING ZERO DETECTING FUNCTION 审中-公开
公开(公告)号：JP2003150371A
公开(公告)日：2003-05-23
申请号：JP2001352531
申请日：2001-11-19
申请人： HITACHI LTD
发明人： YAMADA TETSUYA , ARAKAWA FUMIO
IPC分类号： G06F7/50 , G06F7/00
摘要： PROBLEM TO BE SOLVED: To provide a computing element having a zero detecting function for performing zero detection in parallel with an arithmetic operation and for quickening the zero detection. SOLUTION: Pieces of data (a), a b and carry-in cin are defined as input and an addition result s and a zero detection result are outputted. The computing element is constituted of a carry look-ahead addition/subtraction circuit and a zero detection circuit. Since the sum of (a) and b is zero when the addition result is zero, conformity decision between a result of inverted +1 increment of (a) and b is performed and since difference between (a) and b is zero when a subtraction result is zero, the conformity decision between (a) and b is performed. A zero detection signal is constituted of an OR gate 40 for 1 increment of an addition, an inverted exclusive OR (XNOR) gate 41 for conformity decision of the respective digits and an AND gate 42 for totaling all the digits. Since the zero detection is executed in parallel with the addition, its speed is high in comparison with a case that the zero detection is executed after the addition. A logic is shared between an addition circuit and the zero detection circuit and logical scale is reduced by using a sum signal (Q) of the addition of an input cell (IN) 31 in the zero detection circuit.

18. 发明专利

JP2002149400A SIMD ARITHMETIC SYSTEM CAPABLE OF DESIGNATING PLURAL REGISTERS 失效
公开(公告)号：JP2002149400A
公开(公告)日：2002-05-24
申请号：JP2000340239
申请日：2000-11-08
申请人： HITACHI LTD
发明人： SHIMIZU TATEHISA , ARAKAWA FUMIO
IPC分类号： G06F7/38 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/34 , G06F9/38 , G06F15/80 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To reduce a factor for preventing SIMD operation effects, such as data arrangement in a register in the acceleration of a SIMD processor. SOLUTION: Many pieces of data can be supplied to a data arrangement operation pipe 211 and a data arrangement operation can be fast carried out by dividing a register file into four banks so as to designate a plurality of registers with one operand to simultaneously access four registers. It is also possible to efficiently arrange a large amount of data to be supplied by defining a new data pack instruction/data unpack instruction/data rearrangement instruction. It is further possible to define a product-sum operation instruction by making the best use of the parallelism of a SIMD because of the above characteristic.

19. 发明专利

JP2001273054A DATA PROCESSING DEVICE HAVING LATCH CIRCUIT 失效
公开(公告)号：JP2001273054A
公开(公告)日：2001-10-05
申请号：JP2000088495
申请日：2000-03-24
申请人： HITACHI LTD
发明人： HAYASHI TOMOICHI , ARAKAWA FUMIO
IPC分类号： G06F1/24
摘要： PROBLEM TO BE SOLVED: To improve the usual defect that it is impossible to directly input as a select signal a latch output, which is not decided under power-on, in order to give an input without flowing the through-type current, when a value is inputted into the select signal of the selector (function block 20) in which a bus-transistor is used. SOLUTION: In the case that the outputs 121a-121b of the latch circuits 120a-120b are not valid as the select signal of the selector, when the data are being held, the output-judging circuit 110 changes the latch value to the effective value as the select signal. Therefore, the present invention makes it easy to design a high speed data processing device, since the output value from the latch, which is not initialized under power-on, can be directly inputted as the select signal of the selector.

20. 发明专利

JPH10340589A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10340589A
公开(公告)日：1998-12-22
申请号：JP15185897
申请日：1997-06-10
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： ISHIBASHI KOICHIRO , ARAKAWA FUMIO , NARITA SUSUMU , SHINPO TOSHINOBU
IPC分类号： G06F15/78 , G06F12/10 , G11C15/04
摘要： PROBLEM TO BE SOLVED: To realize a high speed, small rear table look aside buffer(TLB) by connecting the prescribed subdetecting line and the main detecting line through the conduction of a part or the whole of corresponding MOS switches at the time of associated operation and executing only comparing operation of associated memory of prescribed bit. SOLUTION: The electric potentials in the common detecting line are compared with a reference voltage Vref, the potential difference of both of the electric potentials is amplified by a differential amplifier 1, and the result of comparison is outputted. The process bit to store the number of process is connected to a process coincidence detecting line, which is compared with the update pulse and the result is kept in the Cs bit. The update pulse is asserted when the content of process bit is rewritten, and the result is stored in the Cs bit. By such a constitution, it becomes available to separate the process coincidence detecting line and the common detecting line and to decrease the parasitic potential of common detecting line, and thus the comparing operation obtained by amplification of electric potential of common detecting line is made into high speed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式