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11. 发明专利

JPH114265A AMPLIFIER, IDENTIFICATION DEVICE, OPTICAL RECEIVER AND BURST OPTICAL TRANSMISSION SYSTEM 失效
公开(公告)号：JPH114265A
公开(公告)日：1999-01-06
申请号：JP15635997
申请日：1997-06-13
申请人： HITACHI LTD
发明人： HASEGAWA ATSUSHI , YAMASHITA TAKESHI
IPC分类号： H03F3/45 , H04B10/07 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69 , H04L25/03 , H04L25/06 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To make it possible to extend a linear range from an output signal upper bound down to an output signal lower bound of a first differential amplifier by provid ing a second differential amplifier, which makes an output of the first peak detection circuit as a negative phase input, makes a lower limit voltage of the first differential amplifier a positive phase input and makes the output a negative phase input of the first differential amplifier between the output of the first peak detection circuit and the first differential amplifier. SOLUTION: A first differential amplifier 1 amplifies an input signal (a) consisting of signals '1' and '0', and outputs a positive phase output (b) and a negative phase output (c). A first peak detection circuit 2 detects the negative phase output (c) of the first differential amplifier 1 corresponding to '0' of the input signal (a). A second differential amplifier 3 is provided to make an output of the first peak detection circuit 2 a negative input, a reference voltage (d) that is linear motion upper bound voltage of the first differential amplifier 1 a positive phase input and an output the negative phase input of the first differential amplifier 1. Thus, an operation range can be extended up to a linear operation range of the first differential amplifier 1 without having recourse to a direct current.

12. 发明专利

JPH08249230A DATA PROCESSOR 失效
公开(公告)号：JPH08249230A
公开(公告)日：1996-09-27
申请号：JP451496
申请日：1996-01-16
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NISHIMUKAI TADAHIKO , HASEGAWA ATSUSHI , UCHIYAMA KUNIO , KAWASAKI IKUYA , HANAWA MAKOTO
IPC分类号： G06F9/38 , G06F12/08
摘要： PURPOSE: To ensure correspondence between the address of information held in a cache memory and the actual address of a main memory by invalidating an instruction cache memory corresponding to the changeover of the address space of an address conversion mechanism. CONSTITUTION: This data processor 1 is provided with an instruction address generation part 32 for generating instruction addresses, the instruction cache memory 31 for storing the plural instruction addresses and plural instructions corresponding to them and an instruction decoder 35 for decoding the instructions read from the cache memory 31 corresponding to the instruction addresses generated from the instruction address generation part 32. In the data processor, there is a possibility that the address of the information held by the cache memory 31 and the actual address of the main memory 5 become different at the time of switching the address space on the main memory 5 to the different address space. So as to solve the contradiction, the data processor 1 issues a purge instruction beforehand and invalidates the cache memory 31.

13. 发明专利

JPH08102651A BURST LIGHT RECEIVING CIRCUIT 失效
公开(公告)号：JPH08102651A
公开(公告)日：1996-04-16
申请号：JP23876394
申请日：1994-10-03
申请人： HITACHI LTD
发明人： SUZUKI MUNETOSHI , HASEGAWA ATSUSHI
IPC分类号： H03K17/78 , H03F3/08 , H04B10/07 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/67 , H04B10/69 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PURPOSE: To expand a light input operation range by selecting an optimum output out of plural outputs amplified and identified by plural amplifying/ identifying circuits by controlling a switch circuit. CONSTITUTION: A light signal received by a light receiving element 1a is current- voltage converted and amplified by an amplifier circuit 1b and outputted from a preamplifier circuit 1. The output of the circuit 1 is inputted to the switch circuit 2. The circuit 2 controls the selection of outputs from the circuit 2 by a control signal 3 including each signal source setting distance information or the like applied from the external of a burst light receiving circuit. Plural amplifying/identifying circuits 4 connected to the post stage of the circuit 2 hold individual identification reference potential levels in accordance with the level of input amplitude and are provided with an amplification factor capable of obtaining fixed output amplitude at the time of inputting a signal. Although various light input signal amplitude levels are time-dividedly inputted, outputs from respective circuits 4 have the fixed output amplitude.

14. 发明专利

JPH07283425A LIGHT TRANSMISSION/RECEPTION MODULE 失效
公开(公告)号：JPH07283425A
公开(公告)日：1995-10-27
申请号：JP6923194
申请日：1994-04-07
申请人： HITACHI LTD
发明人： YAMAMOTO HIROSHI , HASEGAWA ATSUSHI
IPC分类号： G02B6/42 , H01L31/0232 , H01L33/48 , H01S5/00 , H01L33/00 , H01S3/18
摘要： PURPOSE:To receive light with smaller number of openings than the number of openings of an optical fiber by the optical fiber by spreading the spacing between a transmission IC including a light emission element and an optical fiber incidence end face as compared with the spacing between a reception IC and the optical fiber irradiation end face. CONSTITUTION:Second and fourth lead pins 6 of a transmission side IC1 are bent forward by the lead pitch and first and third lead pins 6 of a reception side IC3 are bent backward, thus shifting a light emission surface 4 and a light reception surface 5 of an IC forward or backward by the width of lead pitch of the lead pins 6 without changing the width and row of the lead pitch. Therefore, since a fiber end face 8 of a connector 7 in one piece for transmission and reception is mated to a same surface for both transmission and reception sides by a gap 9 for achieving the same height, the light emission surface 4 of the transmission side IC and the fiber end face 8 are spaced. By increasing the distance between the optical fiber incidence end face of the transmission IC and the optical fiber irradiation end face of the reception IC, light with a smaller number of openings than the original number of openings of optical fibers can be taken into the optical fiber.

15. 发明专利

JPH07105173A DATA PROCESSOR 失效
公开(公告)号：JPH07105173A
公开(公告)日：1995-04-21
申请号：JP24426593
申请日：1993-09-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , ITOU YOSHITAKA , HASEGAWA ATSUSHI , HAYAKAWA AKIO , HAYASAKA TOSHIMI
IPC分类号： G11C11/407 , G06F1/08 , G06F12/00 , G06F15/78
摘要： PURPOSE:To obtain a single-chip microcomputer-incorporated type clock oscillation circuit which generates a clock facilitating easily interfacing a synchronous DRAM by generating clock pulses which are out of phase with clock pulses of a single-chip microcomputer and interfacing the synchronous DRAM. CONSTITUTION:A clock pulse generator CPG21 can select clock modes 0-6 according to combinations of three clock mode terminals MD0-MD2. When the clock modes 0 to are selected, clocks which has cycles equal to, and twice and four times as long as those of an inputted clock can be used as an internal clock by a PLL circuit 212. In, for example, the test mode 1, the external clock is inputted to the PLL circuit 212 from an input terminal EXTAL and its output is inputted to a PLL circuit 213, which is put in operation in 90 deg. out-of-phase relation with the input clock. At this time, a clock which is inputted from an input/output terminal CK10 to the PLL circuit 213 is outputted.

16. 发明专利

JPS6472237A ADDRESS CALCULATION SYSTEM 失效
公开(公告)号：JPS6472237A
公开(公告)日：1989-03-17
申请号：JP22833787
申请日：1987-09-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： UMINAGA MASAHIRO , HASHIMOTO KOJI , KAWASAKI IKUYA , HASEGAWA ATSUSHI , SAKAMURA TAKESHI , AKITA HIDEHIKO
IPC分类号： G06F9/26 , G06F9/22 , G06F9/32
摘要： PURPOSE:To realize the multi-directional branching jobs with an unconditional branching instruction (JMP instruction) by designating an address calculation part of a CASE instruction separated from the function of said CASE instruction when the branch address of the JMP instruction is designated. CONSTITUTION:A main memory 510 includes a machine word program 511 and a data area 512. A CPU 520 gives an access to the memory 510 and at the same time calculates an address that receives an access by an instruction of the program 511 to refer to and replace the value of the area 512. Thus the CPU 520 performs the data processing. Then an address calculation part of a multi-directional branching instruction (CASE instruction) is separated from the function of a CASE instruction and added into the function of the operand address calculation. Thus the CASE instruction is carried out by a JMP instruction.

17. 发明专利

JPS6441041A MICROPROCESSOR 失效
公开(公告)号：JPS6441041A
公开(公告)日：1989-02-13
申请号：JP19621587
申请日：1987-08-07
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , HASHIMOTO KOJI , KAWASAKI IKUYA , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO
IPC分类号： G06F9/30 , G06F9/46 , G06F12/00 , G06F12/02
摘要： PURPOSE:To retrieve a queue at a high speed by using a queue retrieving instruction and its preceding register setting instruction to obtain the head address of a desired entry. CONSTITUTION:A queue searching instruction includes the operation designating parts OP1 and OP2 storing operation codes, an end condition designating part EC which designates the end conditions of the instruction, a size designating part Sz which shows the comparison value, an M bit showing the presence/ absence of masks of bits Bi and R6 which designate the instruction forms, an E bit showing the end value of a queue, and a U bit showing the searching direction. Then the head address of a retrieving start entry needed for retrieval of the queue is supplied previously to a prescribed register together with the comparison value, i.e., the selecting conditions, and the offset value of the retrieval data stored in an entry. Then the retrieving instruction of the queue is carried out. As a result, the head address of a desired entry is obtained by a queue retrieving instruction and its preceding register setting instruction. Thus a queue is retrieved at a high speed.

18. 发明专利

JPS63238646A MICROPROCESSOR 失效
公开(公告)号：JPS63238646A
公开(公告)日：1988-10-04
申请号：JP28535287
申请日：1987-11-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HANAWA MAKOTO , NISHIMUKAI TADAHIKO , HASEGAWA ATSUSHI
IPC分类号： G06F9/38 , G06F12/08
摘要： PURPOSE:To curtail the overhead time required for a cache retrieval, by executing a hit decision by using a result of holding, at the time of executing an access to continuous addresses, and executing immediately an access to an external memory at the time of a mishit. CONSTITUTION:At the time of executing sequentially an access to plural continuous data areas, and at the time of retrieving the data area shown selectively first in its line by a signal of the remaining bit of a tag address, information of a flag of other data area is held in a holding means, and as for the data area of its line shown selectively thereafter by other signal of the remaining bit, a hit decision of a cache memory is executed by the information of the flag held in the holding means. Accordingly, at the time of retrieving other data area than the data area which is brought to an access first, it is unnecessary to execute minutely a cache retrieval, and by using a result of holding, a decision of hit/mishit can be executed immediately, therefore, the overhead time required for the cache retrieval can be curtailed.

19. 发明专利

JPS6083117A MEMORY CIRCUIT AND ITS USE 失效
公开(公告)号：JPS6083117A
公开(公告)日：1985-05-11
申请号：JP19077083
申请日：1983-10-14
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： YAMADA SHIGETAKA , HASEGAWA ATSUSHI , ITOKAZU TOSHIO , HONMA KAZUHIKO
IPC分类号： G06F12/16 , G06F1/26 , G06F1/28 , G11C29/52
摘要： PURPOSE:To decide whether a short break is given to the power supply of a memory circuit by providing a memory cell consisting of asymmetrical flip-flops at a specific address of the memory circuit. CONSTITUTION:A memory 2 which receives an access from a specific address consists of asymmetrical flip-flops. Then 1 is written to said flip-flops in an initialization mode. Then the power supply is cut off to a CPU1 and therefore the CPU1 is set under a pause mode. Then this CPU1 is started again and reads the contents of the above-mentioned specific address to check whether the value of the read-out contents is 1 or 0. Then the power supply is cut off temporarily to the memory 2. When the power is supplied again to the memory 2, the value of the flip-flops is set at 0 because of their asymmetrical structure. Thus it is decided that the contents of the memory 2 are not normal.

20. 发明专利

JPS6080193A MEMORY SYSTEM 失效
公开(公告)号：JPS6080193A
公开(公告)日：1985-05-08
申请号：JP18691983
申请日：1983-10-07
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HASEGAWA ATSUSHI , HONMA KAZUHIKO
IPC分类号： G06F12/06 , G11C8/12 , G11C7/00
摘要： PURPOSE:To give an access to each memory block at the optimum timing by setting the operating time of writing/reading to each memory block after measuring a prescribed pulse. CONSTITUTION:A decoder 1 which receives a system address signal from a bus AB detects an access to a high-speed memory 6 or a low-speed memory 7. The detection outputs m1 and m2 are used as selection signals of a selector 4. The initial value T1 or T2 given from a memory 2 or 3 is loaded to a shift register 5 by a timing signal phi1 given from the decoder 1. The 7th-10th output signals D7-D10 of the register 5 are supplied to a timing detecting circuit consisting of AND gates G1-G4. The output signals CS1 and CS2 of gates G2 and G3 are used as chip selection signals of the memories 6 and 7 respectively.

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