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11. 发明专利

JPS6324731A DATA TRANSMISSION CIRCUIT 失效
公开(公告)号：JPS6324731A
公开(公告)日：1988-02-02
申请号：JP16851786
申请日：1986-07-17
申请人： FUJITSU LTD
发明人： MIKAMI TAKU
IPC分类号： H04J1/00
摘要： PURPOSE:To reduce deterioration in communication quality, and the possibility of malfunction due to voice by generating a minimum shift keying signal within a sound lower band area by an input data, performing the frequency modulation of a carrier by a signal in which frequency division multiplex is performed on the above signal, and the sound, and sending it to the outside. CONSTITUTION:In a minimum shift keying modulator 10, an MSK signal can be obtained by applying minimum shift keying on the output frequency of a subcarrier generated at a subcarrier generator 13 by an input data. Since the spectrum of the MSK signal is distributed only in a narrow band area, a request for a filter, or a modulator can be loosened than ever. The MSK signal, after being frequency division-multiplexed with the voice by a frequency division multiplexing means 11, modulates the carrier by a modulator 12, and is sent to the outside. In other words, since the data is converted to the MSK signal, and it is inserted to the sound lower band area, and is transmitted, the possibility of deterioration in the call quality, or the malfunction is reduced and furthermore the circuit constitution can be miniaturized.

12. 发明专利

JPS62166618A WIDE-BAND DIGITAL PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPS62166618A
公开(公告)日：1987-07-23
申请号：JP815386
申请日：1986-01-20
申请人： FUJITSU LTD
发明人： SATO YUICHI , MIKAMI TAKU
IPC分类号： H03L7/06
摘要： PURPOSE:To make the titled circuit applicable to an input signal ranging over a wide frequency range, by switching or changing the frequency generated by a reference frequency generating means so that a DPLL circuit can be clocked to an input signal when an out-of-synchronism detecting means detects the out of synchronism of the DPLL circuit. CONSTITUTION:The 1st loop is composed of a phase comparing means 3, variable frequency dividing means 2, and a feedback path 5 which feeds back the output of the means 2 to the input of the phase comparing means 3. The 2nd loop is constituted of the phase comparing means 3, an out-of-synchronism detecting means 4, a reference frequency generating means 1, the variable frequency dividing means 2, and the feedback path 5 which feeds back the output of the means 2 to the input of the phase comparing means 3. When the out-of- synchronism detecting means detects that a state where the 1st loop is not locked continues, the 2nd loop switches or changes the output frequency of the reference frequency generating means 1 in accordance with the direction, in which the frequency of an input signal is deviated from the 1st loop locking range, so that the 1st loop can be locked to the frequency of the input signal.

13. 发明专利

JPS6149504A Sine wave signal generating circuit 失效
标题翻译：正弦波信号发生电路
公开(公告)号：JPS6149504A
公开(公告)日：1986-03-11
申请号：JP17115184
申请日：1984-08-17
申请人： Fujitsu Ltd
发明人： TODA YOSHIFUMI , MIKAMI TAKU
IPC分类号： H04Q1/45 , H03B28/00 , H04L27/26 , H04M1/50 , H04M19/02
摘要： PURPOSE: To eliminate the need for a network, decoder, etc., and to simplify the circuit constitution by setting a binary data sequence corresponding to a half- cycle sine wave signal from parallel input terminals of a shift register, and shifting the data with the output signal of a frequency dividing circuit as a clock signal.
CONSTITUTION: When 16-bit binary data is set in the shift register 6 through parallel input terminals P and 697Hz is set by a setting circuit 3, the frequency dividing circuit 2 outputs a clock signal of (697×16×2)Hz. The register 6 is put in shifting operation with this signal and a pulse signal is outputted from its output terminal Q. This signal is converted by integration 8, and further converted by an LPF5 to obtain a positive half-cycle sine wave. Simultaneously, the serial output of the register 6 is inverted 7 and inputted to the serial input terminal D of the register 6 to obtain a negative half-cycle sine wave, so that the sine wave signal of frequency set by the circuit 3 is outputted continuously and similarly thereafter.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了消除对网络，解码器等的需要，并且通过设置与移位寄存器的并行输入端子的半周期正弦波信号相对应的二进制数据序列来简化电路结构，并且将数据与分频电路的输出信号作为时钟信号。构成：当通过并行输入端P和697Hz在移位寄存器6中设置16位二进制数据时，分频电路2输出（697×16×2）Hz的时钟信号。寄存器6通过该信号进行移位操作，并从其输出端子Q输出脉冲信号。该信号由积分8转换，并由LPF5进一步转换以获得正的半周期正弦波。同时，寄存器6的串行输出反相7并输入到寄存器6的串行输入端子D，以获得负半周期正弦波，使得由电路3设定的频率的正弦波信号被连续输出并在此之后。

14. 发明专利

JPS6090438A DIGITAL MOBILE RADIO RELAY SYSTEM 失效
公开(公告)号：JPS6090438A
公开(公告)日：1985-05-21
申请号：JP19862983
申请日：1983-10-24
申请人： FUJITSU LTD
发明人： YAMADA KATSURA , TODA YOSHIFUMI , OKA NOBUYUKI , MIKAMI TAKU
IPC分类号： H04B7/15 , H04B7/26 , H04K1/00
摘要： PURPOSE:To prevent the difficulty of communication between subscribers due to the increase in the level of secrecy by providing a ciphering radio communication system with a means which distributes a normal secret code for data communication to a repeater station side. CONSTITUTION:In a scrambling and descrambling type radio communication system which enciphers the contents of a subscriber group and transmits them with a radio wave; a repeater station B which relays a transmit signal from a subscriber station A is provided with normal repeater sets B1-Bn and special repeater sets B1'-Bn'. The special repeater sets B1'-Bn' have monitors and returning means of a format corresponding to a secret code for special operation, and when there is an incoming signal in the format corresponding to the secret code for special operation, a secret code in normal operation is distributed to subscriber stations with this format. Consequently, a failure in communication is prevented even when some subscriber station loses a key.

15. 发明专利

JPS6077540A DIGITAL MOBILE RADIO EQUIPMENT 失效
公开(公告)号：JPS6077540A
公开(公告)日：1985-05-02
申请号：JP18613683
申请日：1983-10-05
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , OKA NOBUYUKI , MIKAMI TAKU
IPC分类号： H04B1/40 , H04B1/3822 , H04J13/00 , H04J13/10 , H04Q7/00 , H04Q7/38 , H04W99/00
摘要： PURPOSE:To eliminate the need for the remembrance of a number of a scramble pattern by allowing automatically a scrambler to select the scramble pattern corresponding to a designated channel number. CONSTITUTION:In providing an automatic changeover mode number, e.g., 160 to a switch 26''' and designating the channel number by a switch 24', the scramble pattern number predetermined in response to the channel number is stored in a memory 25' by an address signal transmitted via a converting circuit 28 and an address circuit 27. When the switch 26''' is switched to the automatic changeover mode number 160, a signal converted into a binary-coded hexadecimal number BCHD is transmitted from a converting circuit 32, this signal is detected by a detector 35, an output of the converting circuit 32 is switched into an output of the memory 25' by the said detection output and the scramble pattern corresponding to the designated channel number is selected automatically by the scrambler 9.

16. 发明专利

JP2000082975A CDMA RECEIVER 失效
公开(公告)号：JP2000082975A
公开(公告)日：2000-03-21
申请号：JP25268798
申请日：1998-09-07
申请人： FUJITSU LTD
发明人： HAGA YOSHINOBU , MIKAMI TAKU
IPC分类号： H04B1/707 , H04B1/7117 , H04B7/26 , H04L7/00 , H04W52/02 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To reduce power consumption and to improve the detection precision of inverse spread start timing. SOLUTION: A reception state detection part (RSSI detection part) 60 detects a reception state. A sampling control part 61 decides the number of over-samples (sampling speed) of a matched filter 58 in accordance with the quality of the reception state. The matched filter 58 operates a correlation value between a received spread data string sampled at the sampling speed and a reference code string (short code). A timing detection part 59 sets timing when the correlation value becomes maximum to be inverse spread start timing. A sampling control part 61 reduces the number of over-samples when the reception state is good, drops the operation speed of the matched filter 58, reduces power consumption, increases the number of over-sampling when the reception state is bad so as to improve the detection precision of inverse spread timing.

17. 发明专利

JPH0553424B2 失效
公开(公告)号：JPH0553424B2
公开(公告)日：1993-08-10
申请号：JP14727887
申请日：1987-06-12
申请人： FUJITSU LTD
发明人： ENDO MAKOTO , MIKAMI TAKU , KOMATSUDA SEIJI
IPC分类号： H03M5/06 , H04L7/00 , H04L25/03 , H04L25/40 , H04L25/49

18. 发明专利

JPH0369458B2 失效
公开(公告)号：JPH0369458B2
公开(公告)日：1991-11-01
申请号：JP6506585
申请日：1985-03-30
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MIKAMI TAKU
IPC分类号： H03L7/06 , H03K5/00 , H04B7/26 , H04W12/00 , H04W24/00 , H04W76/02

19. 发明专利

JPH033429B2 失效
公开(公告)号：JPH033429B2
公开(公告)日：1991-01-18
申请号：JP6506785
申请日：1985-03-30
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MIKAMI TAKU , NIIYAMA MANABU
IPC分类号： H04L7/00 , H04L7/02 , H04L7/033

20. 发明专利

JPH02190010A DIGITAL CRYSTAL OSCILLATOR 失效
公开(公告)号：JPH02190010A
公开(公告)日：1990-07-26
申请号：JP1016589
申请日：1989-01-19
申请人： FUJITSU LTD
发明人： MIKAMI TAKU , MURAYAMA YUKIO , NIKAWA SUSUMU
IPC分类号： H03B5/32
摘要： PURPOSE:To avoid the minute adjustment and to eliminate the need for an A/D converter and a D/A converter by measuring in advance a temperature compensation data, employing the memory storing the said data, and giving a input temperature data and an output temperature compensation data subject to time division in the temperature detection mode and the temperature compensation mode to a successive approximation control section and the D/A converter. CONSTITUTION:Upon the receipt of a temperature detection mode signal, a comparator 5 compares a temperature detection voltage and a comparison reference voltage in terms of analog signals, a successive comparison control section 6 generates a digital output being the result of incriminating successively the reference voltage. A selector 8 sends the output to a D/A conversion part to wake the output an analog comparison reference voltage, sends the voltage to a comparator 5 through a selector 10, and a corresponding temperature compensation data is outputted from a memory 7. When a mode switching signal becomes a temperature compensation mode signal, a selector 9 outputs a temperature compensation data of the memory 7 and it is applied to an oscillation circuit 2, then it generated an output signal having an oscillated frequency subject to temperature compensation. Thus, no fine adjustment is required and neither an A/D converter nor a D/A converter is required.

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