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11. 发明专利

JP2015050393A 半導体装置およびその製造方法有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2015050393A
公开(公告)日：2015-03-16
申请号：JP2013182560
申请日：2013-09-03
申请人：株式会社東芝 , Toshiba Corp
发明人： SUZUKI MARIKO , SAKAI TADASHI , OTA CHIHARU , TAKAO KAZUTO , SHINOHE TAKASHI
IPC分类号： H01L29/861 , H01L21/20 , H01L21/205 , H01L21/329 , H01L21/331 , H01L29/06 , H01L29/16 , H01L29/73 , H01L29/868
CPC分类号： H01L29/1602 , H01L21/02376 , H01L21/02433 , H01L21/02527 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/041 , H01L21/042 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/6603 , H01L29/66037 , H01L29/7325 , H01L29/861 , H01L29/868
摘要：【課題】高い絶縁破壊耐圧を実現する半導体装置を提供する。【解決手段】実施形態の半導体装置は、i型またはp型の第1のダイヤモンド半導体層と、第1のダイヤモンド半導体層上に設けられるn型の第2のダイヤモンド半導体層と、第1のダイヤモンド半導体層と第2のダイヤモンド半導体層とを含むように設けられ、上面が{100}面から?10度以内の面方位を有し、側面が{100}面から ?20度の方向に対し20度以上90度以下傾斜するメサ構造と、側面に設けられ、第2のダイヤモンド半導体層と接し、第2のダイヤモンド半導体層よりn型の不純物濃度が低いn型の第1のダイヤモンド半導体領域と、を備える。【選択図】図1
摘要翻译：要解决的问题：提供一种实现高介电击穿电压的半导体器件。解决方案：一个实施例的半导体器件包括：i型或p型第一金刚石半导体层; 设置在所述第一金刚石半导体层上的n型第二金刚石半导体层; 设置为包括第一金刚石半导体层和第二金刚石半导体层的台面结构，其中顶面具有在{100}面±10度的范围内的平面方向，并且侧面倾斜不小于相对于{100}面的<011>±20度范围内的方向为20度且不超过90度; 以及n型第一金刚石半导体区域，其设置在侧面上并与第二金刚石半导体层接触并且具有比第二金刚石半导体层的n型杂质浓度低的n型杂质浓度。

12. 发明专利

JP2014187203A Rectifier and method for controlling the same 审中-公开
标题翻译：整流器及其控制方法
公开(公告)号：JP2014187203A
公开(公告)日：2014-10-02
申请号：JP2013061140
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAO KAZUTO , OTA CHIHARU , NISHIO JOJI , SHINOHE TAKASHI
IPC分类号： H01L29/868 , H01L25/07 , H01L25/18 , H01L29/861
CPC分类号： H02M7/06 , H02M1/08 , H02M1/088 , H02M2001/327 , H03K17/08148 , H03K17/12 , H03K17/74
摘要： PROBLEM TO BE SOLVED: To provide a rectifier and a method for controlling the same, capable of obtaining a stable rectification operation and high reliability.SOLUTION: A rectifier according to an embodiment includes a rectifying element, a control element, and a control unit. The control element is connected in series to the rectifying element. A resistance value of the control element varies with a control signal. The control unit generates the control signal for changing the resistance value according to change in the current flowing in the rectifying element. A method for controlling the rectifier including a rectifying element and a control element whose resistance value varies with the control signal connected in series to the rectifying element according to an embodiment comprises the steps of: detecting a current flowing in the rectifying element; and giving the control signal for changing the resistance value according to the change in the current to the control element.
摘要翻译：要解决的问题：提供一种整流器及其控制方法，能够获得稳定的整流运行和高可靠性。解决方案：根据实施例的整流器包括整流元件，控制元件和控制单元。控制元件与整流元件串联连接。控制元件的电阻值随控制信号而变化。控制单元根据流过整流元件的电流的变化产生用于改变电阻值的控制信号。一种用于控制整流器的方法，包括整流元件和控制元件，其电阻值随着根据实施例的整流元件串联连接的控制信号而变化，包括以下步骤：检测在整流元件中流动的电流; 并且根据与控制元件的电流变化，给出用于改变电阻值的控制信号。

13. 发明专利

JP2008251772A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008251772A
公开(公告)日：2008-10-16
申请号：JP2007090297
申请日：2007-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , NISHIO JOJI , SHINOHE TAKASHI , KONO HIROSHI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a termination structure of a Schottky electrode by which a stable breakdown voltage is realized. SOLUTION: The semiconductor device has a semiconductor substrate 1 of a first conductivity type, a semiconductor layer 2 of a first conductivity type which is formed on the semiconductor substrate 1 and has an active region and an element termination region surrounding it, a first electrode 7 which is formed on the surface of the active region of the semiconductor layer 2 and forms a Schottky barrier against the semiconductor layer 2, a second electrode 10 which is formed on the backside of the semiconductor substrate 1, a first semiconductor region 3 of a second conductivity type which is formed from the end of the active region toward the element termination region, a second semiconductor region 4 of a second conductivity type which is formed under the end of the first electrode 7 on the inner surface of the first semiconductor region on the surface of the semiconductor layer 2 and a third electrode 11 which is electrically connected with the first electrode 7 on the second semiconductor region 4 and formed separately from the active region, and formed of a material different from that of the first electrode 7. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供实现稳定击穿电压的肖特基电极的端接结构。解决方案：半导体器件具有第一导电类型的半导体衬底1，第一导电类型的半导体层2，其形成在半导体衬底1上并且具有有源区和围绕其的元件终止区，第一电极7，其形成在半导体层2的有源区的表面上，并形成对半导体层2的肖特基势垒;形成在半导体衬底1的背面的第二电极10，第一半导体区域3 第二导电类型的第二半导体区域4，其形成在第一导电类型的第二导电类型的第二半导体区域4上，第二导电类型形成在第一半导体的内表面上的第一电极7的端部下方半导体层2的表面上的区域和在第二半导体上与第一电极7电连接的第三电极11 电导体区域4并且与有源区分开形成，并且由不同于第一电极7的材料形成。版权所有（C）2009，JPO＆INPIT

14. 发明专利

JP2008172008A Sic schottky barrier semiconductor device 有权
标题翻译： SIC肖特彼勒半导体器件
公开(公告)号：JP2008172008A
公开(公告)日：2008-07-24
申请号：JP2007003581
申请日：2007-01-11
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIO JOJI , SUZUKI TAKUMA , OTA CHIHARU , SHINOHE TAKASHI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/1608
摘要： PROBLEM TO BE SOLVED: To provide an SiC Schottky barrier semiconductor device that stably operates without much increase of the reverse leakage current even in the case of a temperature variation.
SOLUTION: The SiC Schottky barrier semiconductor device is provided with a first conduction type SiC semiconductor substrate, a first conduction type semiconductor layer formed on the substrate while having a lower impurity concentration than that of the substrate, an anode electrode, which is formed on the semiconductor layer, forms a Schottky junction with the semiconductor layer, and has a Schottky barrier height of ≤l eV, a plurality of second conduction type junction barrier parts formed on the Schottky interface, and a second conduction type junction termination part formed outside a plurality of junction barrier parts on the Schottky interface. The plurality of junction barrier parts are formed deeper than the junction termination part. An interval between the plurality of junction barrier parts is ≤0.6 times of the depth of the junction barrier part. A relationship between the width w of the junction barrier part and the interval s between the junction barrier parts satisfies s/(w+s)
摘要翻译：要解决的问题：即使在温度变化的情况下，也可提供稳定地工作而不会大大增加反向泄漏电流的SiC肖特基势垒半导体器件。解决方案：SiC肖特基势垒半导体器件设置有第一导电型SiC半导体衬底，形成在衬底上的杂质浓度低于衬底的第一导电类型半导体层，阳极电极形成在半导体层上，与半导体层形成肖特基结，肖特基势垒高度≤1eV，形成在肖特基界面上的多个第二导电型结型势垒部分和形成于第二导电型连接端接部分在Schottky接口上的多个接合阻挡部分之外。多个接合阻挡部分形成得比接合端部更深。多个接合阻挡部分之间的间隔是接合阻挡部分的深度的0.6倍。接合阻挡部分的宽度w与接合势垒部分之间的间隔s之间的关系满足s /（w + s）<0.33。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2014187113A Vapor deposition apparatus and vapor deposition method 审中-公开
标题翻译：蒸气沉积装置和蒸气沉积方法
公开(公告)号：JP2014187113A
公开(公告)日：2014-10-02
申请号：JP2013059830
申请日：2013-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIO JOJI , SHIMIZU TATSUO , OTA CHIHARU , SHINOHE TAKASHI
IPC分类号： H01L21/205 , C23C16/42
CPC分类号： C30B25/14 , C23C16/22 , C30B25/02 , C30B29/36 , H01L21/02634
摘要： PROBLEM TO BE SOLVED: To provide a vapor deposition apparatus capable of easily performing co-doping of a p-type impurity and an n-type impurity.SOLUTION: The vapor deposition apparatus comprises: a reaction chamber; a first gas supply pathway for supplying Si source gas to the reaction chamber; a second gas supply pathway for supplying C source gas to the reaction chamber; a third gas supply pathway for supplying an n-type impurity source gas to the reaction chamber; a fourth gas supply pathway for supplying a p-type impurity source gas to the reaction chamber; and a control part for controlling an amount of the n-type impurity and the p-type impurity source gas at a predetermined ratio and introducing the gas into the reaction chamber. When an element A is used as the p-type impurity and an element D is used as the n-type impurity, a combination of the element A and the element D is at least one combination of Al, Ga or In, N, B and P.
摘要翻译：要解决的问题：提供能够容易地进行p型杂质和n型杂质的共掺杂的气相沉积装置。解决方案：蒸镀装置包括：反应室; 用于向反应室供应Si源气体的第一气体供应路径; 用于向反应室供给C源气体的第二气体供给路径; 用于向所述反应室供给n型杂质源气体的第三气体供给路径; 用于向反应室供给p型杂质源气体的第四气体供给路径; 以及用于以预定比例控制n型杂质和p型杂质源气体的量并将气体引入反应室的控制部分。当使用元素A作为p型杂质并且元素D用作n型杂质时，元素A和元素D的组合是Al，Ga或In，N，B的至少一种组合和P.

16. 发明专利

JP2014130913A Semiconductor device and driving method thereof 审中-公开
标题翻译：半导体器件及其驱动方法
公开(公告)号：JP2014130913A
公开(公告)日：2014-07-10
申请号：JP2012287770
申请日：2012-12-28
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , TAKAO KAZUTO , NISHIO JOJI , SHINOHE TAKASHI
IPC分类号： H01L29/872 , H01L27/04 , H01L27/088 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/868
CPC分类号： H01L23/345 , H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/6606 , H01L29/7803 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of obtaining a stable on-voltage, and a driving method thereof.SOLUTION: A semiconductor device according to an embodiment comprises a first semiconductor region, a second semiconductor region, a first electrode, and a heating unit. The first semiconductor region includes n-type silicon carbide. The second semiconductor region is provided on the first semiconductor region and includes p-type silicon carbide. The first electrode is provided on the first semiconductor region and the second semiconductor region. The heating unit is provided on the second semiconductor region.
摘要翻译：要解决的问题：提供能够获得稳定导通电压的半导体器件及其驱动方法。根据实施例的半导体器件包括第一半导体区域，第二半导体区域，第一电极和加热单元。第一半导体区域包括n型碳化硅。第二半导体区域设置在第一半导体区域上并且包括p型碳化硅。第一电极设置在第一半导体区域和第二半导体区域上。加热单元设置在第二半导体区域上。

17. 发明专利

JP2014045167A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014045167A
公开(公告)日：2014-03-13
申请号：JP2013098662
申请日：2013-05-08
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , NISHIO JOJI , TAKAO KAZUTO , SHINOHE TAKASHI
IPC分类号： H01L29/861 , H01L21/20 , H01L21/265 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/16 , H01L29/47 , H01L29/739 , H01L29/78 , H01L29/868 , H01L29/872
CPC分类号： H01L29/0615 , H01L21/0257 , H01L29/0638 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/6606 , H01L29/7395 , H01L29/7802 , H01L29/8613 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows improving long-term reliability and a method of manufacturing the same.SOLUTION: A semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is a region of a first conductivity type. The second semiconductor region is provided on the first semiconductor region and has a lower impurity concentration than the first semiconductor region. The third semiconductor region is a region of a second conductivity type provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region or on a part of the third semiconductor region, and has larger lattice strain than the third semiconductor region.
摘要翻译：要解决的问题：提供一种能够提高长期可靠性的半导体器件及其制造方法。解决方案：半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域和第四半导体区域地区。第一半导体区域是第一导电类型的区域。第二半导体区域设置在第一半导体区域上，并且具有比第一半导体区域低的杂质浓度。第三半导体区域是设置在第二半导体区域上的第二导电类型的区域。第四半导体区域设置在第三半导体区域或第三半导体区域的一部分上，并且具有比第三半导体区域更大的晶格应变。

18. 发明专利

JP2013183064A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013183064A
公开(公告)日：2013-09-12
申请号：JP2012046503
申请日：2012-03-02
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIO JOJI , OTA CHIHARU , SHINOHE TAKASHI
IPC分类号： H01L29/861 , H01L21/20 , H01L21/265 , H01L21/329 , H01L21/336 , H01L29/12 , H01L29/78 , H01L29/868
CPC分类号： H01L21/02658 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/046 , H01L21/74 , H01L23/544 , H01L29/045 , H01L29/0615 , H01L29/0661 , H01L29/1608 , H01L29/32 , H01L29/6606 , H01L29/66068 , H01L29/8613 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which prevents deterioration in properties due to BPD.SOLUTION: A method of manufacturing a semiconductor storage device according to an embodiment comprises: preparing a hexagonal silicon carbide substrate, injecting ions into the silicon carbide substrate, forming a silicon carbide film on the silicon carbide substrate into which ions are injected by epitaxial growth, and forming a pn junction region in the silicon carbide film.
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件防止由于BPD引起的性能劣化。解决方案：根据实施例的半导体存储器件的制造方法包括：制备六方晶系碳化硅衬底，将离子注入到在碳化硅衬底上形成通过外延生长注入离子的碳化硅膜，并在碳化硅膜中形成pn结区域。

19. 发明专利

JP2012059902A Semiconductor device, and method for manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012059902A
公开(公告)日：2012-03-22
申请号：JP2010201452
申请日：2010-09-08
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , KONO HIROSHI , TAKAO KAZUTO , SHINOHE TAKASHI
IPC分类号： H01L29/861
CPC分类号： H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/868 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a device capable of lowering a loss while maintaining a basic characteristic of a diode.SOLUTION: The semiconductor device in an embodiment comprises a first conductive-type semiconductor substrate, a first conductive-type first semiconductor layer, a second conductive-type first conductor area, a second conductive-type second semiconductor area, a first conductive-type third semiconductor area, a first electrode, and a second electrode. The second conductive-type first semiconductor area is selectively formed at one part on the first semiconductor layer. The second conductive-type second semiconductor area is selectively formed to reach inside the first semiconductor layer at another part on the first semiconductor layer, so as to have a higher concentration of impurities than that of the first semiconductor area. The first electrode is selectively formed on the second and third semiconductor areas. The second electrode is formed to contact a rear face of the semiconductor substrate.
摘要翻译：要解决的问题：提供一种能够在保持二极管的基本特性的同时降低损耗的装置。解决方案：实施例中的半导体器件包括第一导电型半导体衬底，第一导电型第一半导体层，第二导电型第一导体区域，第二导电型第二半导体区域，第一导电型型第三半导体区域，第一电极和第二电极。第二导电型第一半导体区域选择性地形成在第一半导体层的一部分上。选择性地形成第二导电型第二半导体区域，以在第一半导体层的另一部分到达第一半导体层的内部，从而具有比第一半导体区域更高的杂质浓度。第一电极选择性地形成在第二和第三半导体区域上。第二电极形成为接触半导体衬底的后表面。版权所有（C）2012，JPO＆INPIT

20. 发明专利

JP2012059823A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012059823A
公开(公告)日：2012-03-22
申请号：JP2010199982
申请日：2010-09-07
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , SHINOHE TAKASHI , MIZUKAMI MAKOTO , NISHIO JOJI
IPC分类号： H01L29/861 , H01L21/265 , H01L21/28 , H01L29/41 , H01L29/93
CPC分类号： H01L29/1608 , H01L21/02529 , H01L21/26513 , H01L29/47 , H01L29/66136 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a low-loss semiconductor device in which loss caused by ion implantation damage is suppressed.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type which is formed on an upper face of the semiconductor substrate and has an impurity concentration lower than the semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer by epitaxial growth; and a third semiconductor layer of the second conductivity type which is formed on the second semiconductor layer by epitaxial growth and has an impurity concentration higher than the second semiconductor layer. Furthermore, the semiconductor device comprises a recess which is formed on the third semiconductor layer and of which at least a corner between the side face and the bottom face is within the second semiconductor layer. The semiconductor device also comprises a first electrode in contact with the third semiconductor layer, a second electrode which is in contact with the second semiconductor layer in the bottom face of the recess and which is connected to the first electrode, and a third electrode which is in contact with a lower face of the semiconductor substrate.
摘要翻译：解决的问题：提供抑制由离子注入损伤引起的损耗的低损耗半导体器件。解决方案：根据实施例的半导体器件包括：第一导电类型的半导体衬底; 第一导电类型的第一半导体层，其形成在半导体衬底的上表面上，其杂质浓度低于半导体衬底; 通过外延生长在第一半导体层上形成的第二导电类型的第二半导体层; 以及第二导电类型的第三半导体层，其通过外延生长形成在第二半导体层上，并且具有高于第二半导体层的杂质浓度。此外，半导体器件包括形成在第三半导体层上并且其侧面和底面之间的至少角部在第二半导体层内的凹部。半导体器件还包括与第三半导体层接触的第一电极，与凹部的底面中的第二半导体层接触并连接到第一电极的第二电极，以及第三电极，与半导体衬底的下表面接触。版权所有（C）2012，JPO＆INPIT

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